Kane Industries C6713CPU - Manual (Page 19)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 19
2.5.9 DMA
The TMS320C6713 DSP provides an enhanced DMA (EDMA) controller with 16 channels and 16
possible synchronization events. It can be used to transfer data between two locations anywhere in
the address range of the C6713CPU. EDMA transfers can be triggered by software, internal
events, such as timers or serial ports, or by hardware interrupt lines. DMA operations can be
chained, that means the end of one transfer starts the next transfer. This provides a powerful,
flexible way to perform continuous data flow without CPU intervention as well as scatter-gather
transfers. The enhanced DMA can perform element transfers with single cycle throughput in the
case that the source and destination are on two different internal buses and each provides a single
cycle throughput. In this case a maximum data throughput of 300 MWords per second can be
achieved.
Furthermore, there is another, more simplified DMA register set available: the QDMA (quick DMA).
QDMA transfers can be set up within five CPU clock cycles register accesses and can be re-
started with one a single register access.
At the TMS320C6713 DSP the DMA is the only way to perform fast block transfers from or to non-
cached locations.
Detailed information can be found in [4], [6], [12] and [13].