Kane Industries C6713CPU - Manual (Page 38)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 38
TXD
:
This pin is the transmit data output of the RS-232 interface. Output voltage is either -5.5 V (typical)
or +5.5 V (typical). This output can be disabled by putting the RS-232 line driver in shut down
mode, see chapter 3.10.4.
RTS
:
This pin is the ready to send output of the RS-232 interface. Output voltage is either -5.5 V (typical)
or +5.5 V (typical). This output can be disabled by putting the RS-232 line driver in shut down
mode, see chapter 3.10.4. RTS is set to –5.5 V by a pull-up resistor on the line driver input when
the FPGA is not loaded.
RXD
:
This pin is the receive data input of the RS-232 interface. This pin accepts RS-232 signal levels
from –10 V to +10 V. An internal 5kΩ pull down resistor to GND is integrated in the line receiver.
CTS
:
This pin is the clear to send input of the RS-232 interface. This pin accepts RS-232 signal levels
from –10 V to +10 V. An internal 5kΩ pull down resistor to GND is integrated in the line receiver.
The CTS pin can also be used as a reset input. The reset generation is controlled by the PLD (see
chapter 3.10.4)
Pin D30
:
This signal is routed to the FPGA. Usage of the signal requires either an ORSYS board support
package or a custom FPGA design. In default hardware configuration, this signal is pulled high by
a 4.7K
Ω pull-up resistor. Hardware configuration can also be changed to a pull-down resistor, see
chapter 7.2.4 for details.
/HOLD (pin D31):
This signal is routed to the FPGA and to the /HOLD pin of the DSP. If this signal is driven by the
FPGA, it should not simultaneously be driven by an external source via the micro-line
® pin. The
C6713CPU board provides a 10K Ω pull-up resistor on this signal.
/HOLDA (pin D32):
This signal is routed to the FPGA and to the /HOLDA pin of the DSP. This signal is driven by the
DSP so it may not be driven by the FPGA or from the micro-line
® pin. The C6713CPU board
provides a 10K Ω pull-up resistor on this signal.
6.5.5 Connector E
Pins E1 through E9:
These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board
support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as
the FPGA is not loaded.
DR1 / SDA1:
This pin has a dual function:
• If configured for McBSP usage, this pin is the data receive input of McBSP1. All incoming
data from devices, connected to the McBSP1 is communicated via this input pin. If the
receiver port function is not needed, DR1 can also be used as general purpose input.
• If configured for I 2 C interface usage, this pin is the open collector data line for I 2 C interface
1.
DR1 has a 10K Ω pull-up resistor and a 22R series resistor. How to use this pin is described in [4],
[6] and [9].