Kane Industries C6713CPU - Manual (Page 21)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 21
3.2 C6713CPU Address Map
The table below shows how the C6713CPU uses the four CE address spaces of the processor:
address range (hex)
CE space size (bytes) Description
8000 0000 - 83FF FFFF 128MB external RAM (SDRAM)
8400 0000 - 8FFF FFFF
CE0
128MB reserved (mirrored SDRAM)
9000 0000 - 900F FFFF CE1 1MB flash memory (upper or lower half)
9010 0000 - 9017 FFFF 512K PLD register set
9018 0000 - 901F FFFF 512K FPGA register set
9020 0000 - 9FFF FFFF 254M reserved (mirrored flash & registers)
A000 0000 - AFFF FFFF CE2 256M reserved for use by FPGA
B000 0000 - BFFF FFFF CE3 256M reserved for use by FPGA
Table 2: Memory map of the C6713CPU
3.3 Internal fast SRAM
The TMS320C6713 DSP provides a total of 256 KB of internal fast SRAM. The upper 64 KB can
partially or fully be used as level-2 cache. Please refer to [4] for details about cache memory
usage. The lower 192 KB can be used for any purpose. The DSP-internal memory should be used
for application software parts that need very fast memory access. The DSP-internal SRAM can be
accessed via 256 bit bus width, whereas all accesses to on-board memory are limited to 32 bit bus
width. External SDRAM (via EMIF) and DSP-internal SRAM can be accessed simultaneously.
3.4 DSP Peripherals
The DSP peripherals are briefly explained in chapter 2.5 . Their addresses are defined in [4].
3.5 External SDRAM
The external SDRAM of the C6713CPU is mapped into the processor's CE0 address space. This
memory can be used for user applications and/or data storage.
The external SDRAM address space starts at address 8000 0000h, regardless of the memory size
and ends at 8000 0000h + SDRAM size. The upper 1400h bytes of the SDRAM are reserved for
usage by the Flash File System and should not be used for initialized sections (
.text
,
.cinit
, etc.)
of user applications. The external SDRAM is typically used for large buffers and code or data that
is not extremely time-critical. For time-critical code or data, internal fast SRAM should be used.
Please note that using the cache speeds up external SDRAM accesses significantly.
3.6 Flash Memory
The Flash memory is mapped into the processor's CE1 address space, together with PLD and
FPGA registers. The flash size is 2 MB, however the address space for the flash memory is divided
into 2 parts, each of them holds 1 MB of data. The upper and lower segment can be accessed with
the FLASH_A19 bit in the MCR register as described in chapter 3.10. The flash memory can be
programmed in units of sectors, most of them are of 64 KB size, with exception of the first 4
sectors. See [19] for details.
The C6713CPU is shipped with the Flash File System software installed. Therefore, accesses to
the flash memory are handled by the Flash File System and corresponding utilities (see chapter 5
and [24]). Direct accesses to the flash memory from application software are not recommended.
After reset or power up, the DSP boots from flash memory. During the boot process, the Flash File
System software is loaded. The Flash File System software then loads the FPGA(s) and
application software, that is marked as auto-start application and executes it.