Kane Industries C6713CPU - Manual (Page 14)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 14
can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any
clock frequency up to 100 MHz.
Compared to the internal fast SRAM of the DSP chip, the on-board SDRAM is significantly slower.
Therefore it is strongly recommended to use the internal memory of the DSP whenever it is
possible. The internal memory can be used as memory for time critical code and data as well as L2
cache. See [4] for details.
2.3.3 Flash Memory
The C6713CPU uses an MX29LV160BT flash memory for non-volatile storage. The flash memory
is 16 bit wide and can hold up to 2 MB. It is used for permanent storage of software- and FPGA
code.
After reset or power up, the DSP boots from the first address of the flash memory. The DSP
internal boot loader copies the first 1 KB to internal memory to address 0 and executes it. Further
loading is realized by a secondary loader program.
The C6713CPU is always shipped with the Flash File System installed. It handles all flash memory
programming and management of stored data. The Flash File System is automatically booted after
reset or power up. It first initializes the system, then looks for commands from a host on the RS-
232 interface (See [24] for a description of the host side utilities) and then loads the FPGA(s) and a
user program that are selected for auto-boot. Since RS-232 usage on the C6713CPU requires a
loaded FPGA design, the Flash File System already contains a startup FPGA design, which is
loaded during system startup. Later on it will be overwritten when the on-board auto-boot FPGA is
loaded.
2.3.4 PLD
The PLD contains some necessary glue logic of the board. It provides all necessary resources to
run the DSP without a loaded FPGA. It also contains some register that configure board operation.
See chapter 3.10 for a description of the PLD registers,
2.3.5 UART / RS-232 Interface
The RS-232 interface is realized inside the FPGA and is connected to a RS-232 line driver.
Therefore, to use the RS-232 interface, an appropriate FPGA design must be loaded. The RS-232
interface can be used as general purpose communication interface. Functions like fprintf(), and
fgetc()
, etc. are executable by the application program on the micro-line ® C6713CPU, using the
RS-232 interface as a communication channel, e.g. to transfer measurement results to a host
system or to control a connected peripheral device. Another common usage of the RS232 interface
is to output debugging information during testing.
The interface consists of the signals TxD (transmit data), RxD (receive data), RTS (request to
send) and CTS (clear to send). These signals are available at the micro-line
® connector. Please
refer to chapter 6.1 for details. The CTS input signal can also be configured in a way to generate a
system reset on the C6713CPU board.
The UART of the (default) micro-line busmaster BSP can operate at programmable baud rates up
to 1Mbaud.
The RS-232 line driver can be switched into shutdown mode to reduce power consumption. Please
see chapter 3.10.4 for details.
Please note: When using the RS-232 interface in conjunction with a PC that runs Windows 2000 or
XP, the transmit buffer settings of the PC's COM port must be changed on the PC as described for
the Flash File System installation in [24].
2.3.6 Temperature Sensor
The C6713CPU has an onboard temperature sensor with a serial I 2 C-Bus interface in order to
determine the board temperature during operation. The sensor can measure a temperature range
from –25°C up to +85°C with an accuracy of 2 degrees and –55°C up to +125°C with an accuracy
of 3 degrees. If the C6713CPU is operated in an environment where it is exposed to high
temperatures, the temperature sensor can be used to detect over-temperature conditions. The