Kane Industries C6713CPU - Manual (Page 18)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 18
2.5.6 Timers
The TMS320C6713 DSP provides two independent 32-bit general purpose timers. The timers
support two signaling modes and can be clocked by an internal or an external source. Each timer
has a separate input pin and an output pin. Using an internal clock, for example, the timer can
trigger an external A/D converter to start a conversion, or it can trigger the DMA controller to start a
data transfer. If connected to an external digital signal source, the timer can count external events
and interrupt the DSP after a specified number of events.
Each timer input pin TINP0 or TINP1 can either work as timer clock input or be configured for
general purpose digital input. Each timer output pin TOUT0 or TOUT1 can either work as clock
output or be configured for general purpose digital output.
At the TMS320C6713 DSP, the timer signals are shared with the McASP0 port.
On the C6713CPU board, the timer signals are routed to micro-line
® connectors.
Chapter 6.3 contains a detailed listing of connector pin assignments as well as a list of shared
signals. Detailed information how to use the timers can be found in [4] and [6].
2.5.7 Host Port Interface (HPI)
The TMS320C6713 DSP provides a 16 bit wide Host Port Interface (HPI) which can be used by a
host processor to directly access the memory of the DSP. Here, the host device accesses the HPI
as a master and the DSP acts as a slave. The host processor and the DSP can exchange
information via DSP-internal and on-board memory. The host also has direct access to memory-
mapped peripheral registers. Connectivity to the DSP memory space is automatically provided by a
background DMA mechanism. The host device controls the HPI transfers via dedicated HPI
address and data registers which are not accessible for the DSP. Here, the DMA auxiliary channel
connects the HPI to the DSP memory space.
On the TMS320C6713 DSP, the HPI peripherals shares signals with
• McASP1
• GPIO
HPI booting is not supported by default. If HPI booting is required, please contact ORSYS.
HPI operation requires an appropriate FPGA to be loaded, such as [21]. Further information about
the HPI can be found in [4] and [6]. HPI operation is enabled in default hardware configuration.
(see chapter 7.2).
2.5.8 Interrupts
Four maskable and one non-maskable interrupt hardware input lines allow on-board and off-board
hardware devices to interrupt a running program and jump into a dedicated interrupt service
routine. DMA transfers can also be triggered by hardware interrupt lines. Detailed information
about interrupts can be found in [4], [6] and [5].
At the TMS320C6713 DSP, hardware interrupt lines are shared with GPIO signals and McASP
ports.
On the C6713CPU board the DSP interrupt lines EXT_INT4 and EXT_INT5 are directly connected
to the micro-line
® connectors (/EXT_INT4, /EXT_INT5) as well as to the FPGA. The remaining
interrupt lines EXT_INT6, EXT_INT7 and NMI are only connected to the FPGA. Therefore,
EXT_INT6, EXT_INT7 and NMI are typically used for on-board interrupt sources, while EXT_INT4
and EXT_INT5 can be used for both, off-board and on-board interrupt sources. Care must be taken
that /EXT_INT4 and /EXT_INT5 are only driven by a single source, that is either the FPGA or an
external hardware on the micro.-line bus.
The (default) micro-line
® busmaster BSP provides programmable interrupt polarity and routes
EXT_INT[7:6] and NMI to the external connectors sot that /EXT_INT[7:4] and /NMI are available at
the micro-line
® connectors.
For proper interrupt operation, application software must set up the interrupt configuration so that
EXT_INT[7:4] are falling edge triggered. this can be done either by writing to the EXTPOL register,
or by using an appropriate DSP/BIOS configuration file (see [20]).