Reset generator and watchdog, External flags (xf signals), Power supply of the board – Kane Industries C6713CPU User Manual

Page 15: Status led's, Caution

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H

ARDWARE

R

EFERENCE

G

UIDE

MICRO

-

LINE

®

C6713CPU

Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 15


DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the
sensor. Software drivers for the temperature sensor are included in the development kits, see [20]
for details. Further information can be found in [18].
The temperature sensor is connected to the PLD by a separate I

2

C interface. It does not use the

I

2

C interfaces of the DSP. The temperature sensor can be accessed by the I

2

C bus control register

(see chapter 3.10.5).

2.3.7 Reset Generator and Watchdog
The C6713CPU board provides a triple voltage supervising reset generator which generates a
defined reset pulse in case of one or more of the following events:

• power

up

• software reset (via the module control register; see chapter 3.10)

• the /RESETIN pin is active (low)

• one of the supply voltages drops below a certain limit

• the reset generator's watchdog timer is enabled and has expired

• The reset function of the RS232 CTS line is activated and CTS is active.


During the reset pulse the micro-line

®

signals /RESETOUT and RESETOUT are activated.

The reset generator circuit has a watchdog timer that causes a reset if it is not reset periodically by
software. The watchdog timer is disabled by default, thus no resets will be generated and the
watchdog timer does not need to be reset by software.
Enabling the watchdog timer and resetting it is described in chapter 3.10.7.

2.3.8 External Flags (XF signals)
The C6713CPU provides two dedicated general-purpose I/O pins that can be configured as either
inputs or outputs. When configured as an output, the user can write to a PLD register to control the
state driven on the output pin. When configured as an input, the user can detect the state of the
input by reading the state of a PLD register. Please refer to chapter 3.10 for a description on how
to control the XF pins. Please note that also some of the on-chip interfaces of the DSP, such as the
McBSP, can be used as general purpose I/O.

2.3.9 Power Supply of the Board
The C6713CPU must be supplied with a voltage of 3.3 V. It is not designed for 5V supply! Please
refer to chapter 7.1 for connection details.

CAUTION:

The C6713CPU is not protected against reversed voltage. Please be careful when connecting the
power supply to the board. Applying reversed voltage will damage the board!

The following voltages are generated internally on the C6713CPU by highly efficient switched
mode voltage regulators:

• 1.4 V supply voltage for the processor core

• 1.25 V supply voltage for the FPGA core

2.4 Status

LED's

On the C6713CPU there are two groups of LED's:

• two user programmable LED's controlled by the PLD

• one user programmable LED controlled by the FPGA

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