Kane Industries C6713CPU - Manual (Page 48)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 48
7.2.6 Configuring CLKS1 / SCL1 Termination
By default, a 10k
Ω pull-down resistor (R65) is installed for CLKS1 operation. This configuration is
suitable for McBSP #1 operation. For usage of I 2 C interface #1, R65 must be removed and R67
must be mounted with a 10k Ω pull-up resistor.
R65
R67 pin used as
mounted with 10k Ω (default) not mounted (default) CLKS1
not mounted mounted with 10k Ω SCL1
7.2.7 Configuring FPGA I/O Behavior When FPGA is not Loaded
Before the FPGA is loaded, all FPGA I/O pins are pulled high by default. The HSWAP_EN input of
the FPGA determines whether or not weak pull-up resistors are enabled in an unloaded state.
HSWAP_EN = 1 disables the pull-up resistors while HSWAP_EN = 0 (default) enables the pull-up
resistors. The default setting is to have pull-up resistors enabled and is required by the Flash File
System. Please contact ORSYS if this setting has to be changed.
7.3 Signal Levels and Loads
7.3.1 Input Voltage Levels for non-FPGA Signals
All digital logic input signal levels are 0 to +0.8V for logic low and +2.0V to +3.3V for logic high and
can be driven by an output of one of the following logic standards
• 3.3V LVTTL
• 2.5V CMOS
Exceptions are the RS-232 interface signals. Their voltage levels are listed in the individual pin
description (chapter 6.5.4).
CAUTION:
Do not apply voltages higher than 3.3V to any pin of the micro-line ® connector (except RS-232
pins).
7.3.2 Output Voltage Levels for non-FPGA Signals
All output signals of the C6713CPU (except the RS-232 interface) typically drive a logic high signal
level of +3.3V. They can drive inputs of one of the following logic standards:
• 3.3V LVTTL
• 2.5V CMOS
7.3.3 Allowed Output Loads
The maximum output load on the micro-line
® connector depends on the type of the output. The
micro-line ® pins can be divided into four categories regarding source, buffered or non-buffered.
1. The non-buffered outputs are directly connected to the DSP. The output pins are on micro-
line ® connectors E10..E25 and E28, E29 (McBSP, McASP, I 2 C and timer interfaces). For
these sensitive signals please refer to the recommended operating conditions in [4].
2. Outputs driven by the PLD (/RESETOUT, RESETOUT, XF0, XF1). These outputs should
not drive loads higher than 200pF and ±8mA.
3. FPGA signals. For these signals, please refer to the BSP or FPGA development
documentation.
4. Signals buffered by bus drivers (HD0 to HD15). These outputs can drive loads of 24mA
(high level) and 48mA (low level) and typically 40pF. Loads above 80pF should be avoided.
The maximum load should be limited to not more than 5 signals.