Kane Industries C6713CPU - Manual (Page 29)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 29
4 Boot Process and Default Setup of the C6713CPU
After reset or power up the C6713CPU boots the Flash File System from flash memory. The Flash
File System first checks, if a command from a host PC on the RS-232 interface is pending. If a
command is pending, if performs the desired function (see [24]). If no command is present, it looks
for files that are marked as auto-boot FPGA and a file that is marked as auto-boot application
program. All of them are loaded and started. The Flash File System already sets up clock and
EMIF settings of the TMS320C6713 DSP. The default settings can be used by the user application,
so the user does not need to change the settings. The default settings are listed below:
Parameter
Value
CPU clock 225 MHz / 300 MHz
Peripheral clock 112.5 MHz / 150 MHz
EMIF clock 90 MHz / 100 MHz
EMIF global control hold allowed, no output on CLKOUT[2:1]
EMIF CE0 32 Bit SDRAM
EMIF CE1 asynchronous 16 bit, 2-9-2 clocks read/write, 2 clock turnaround
EMIF CE2 asynchronous 32 bit, 3-10-3 clocks read/write, 2 clocks turnaround
EMIF CE3 asynchronous 16 bit, 3-10-3 clocks read/write, 2 clocks turnaround
Table 9: Default clock and EMIF settings of the C6713CPU
In case of multiple FPGA peripheral systems the C6713CPU is also capable to boot up to 1023 off-
board FPGAs with a defined booting sequence. In that case each off-board FPGA is marked with
individual boot- address and -handshake information, as well as a certain boot-sequence number.