Kane Industries C6713CPU - Manual (Page 28)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 28
WDG_RST:
The WD_RST pin of the PLD is connected to the watchdog input of the reset generator. If the
watchdog is enabled the WD_RST pin must be set to 1 at least once per second. This must be
done by writing a 1 to the WDR_RST bit of this register. The WDR_RST bit is self-clearing.
Application software should access this bit from within a function that must be periodically, usually
the main loop. It should not be accessed from an interrupt service routine.
WDG_EN:
If the WDG_EN is set to 1, the on-board watchdog is enabled. A reset will be generated, whenever
the watchdog timer expires. This bit is set to 0 after a hardware reset and can only be set but not
be cleared by application software. Thus, if the watchdog is enabled, there is no way to disable it.
3.10.8 Version Register (VER)
This register contains the PLD version. The version number is encoded as a four bit number and is
read-only. It may be updated due to changes of the PLD code or changes of the C6713CPU
hardware. Application software can read the version number in order to determine the version of
the PLD code.
7 4 3 0
VERSION RESERVED
r
Applies to VERSION
PCB PLD
Comment
0 n/a n/a reserved for internal use
1 V1.0 V1.0 First public release
2 .. F n/a n/a reserved for future versions of
this board
Table 8: Version register encoding