Kane Industries C6713CPU - Manual (Page 13)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 13
interfacing over for the majority of the micro-line
® connector pins. The user is no longer restricted
to a fixed I/O logic.
The FPGA has access to the following signal groups:
• DSP EMIF (data bus, address bus, control signals)
• micro-line ® connectors
• JTAG interface
• DSP interrupts
• RS232 line driver
The figure below gives an overview, how the FPGA is connected on the C6713CPU board. The
numbers shows the number of signals for each connection. The description of the micro-line
®
connectors in parentheses show the classic functions, as they are implemented by the micro-line ®
busmaster BSP (see [21]) and also by classic micro-line ® CPU and peripheral boards without
FPGA.
Figure 4: FPGA connections overview
After power up or hardware reset, the FPGA is automatically cleared and has to be loaded before it
starts operation. This can be done manually by application software or automatically by the Flash
File System of the C6713CPU. The FPGA can be loaded at any time and can also be reloaded
with a different configuration during runtime without the need to power-off or reset the whole board.
During system startup, a FPGA design is loaded by the Flash File System (see chapter 2.3.3). This
FPGA design leaves all external pins passive, except the RS-232 interface. For a more detailed
description of the FPGA signals, please refer to the documentation of the micro-line busmaster
BSP [21] or FPGA development [22].
2.3.2 External Memory (on-board SDRAM)
The C6713CPU uses 32-bit wide SDRAM with 32 or 64 MB in standard off-the-shelf versions and
up to 128 MB on request. This provides a large memory space for storage of program code or
data. The memory access timings are based on the EMIF clock which is initialized to 90 MHz
(225 MHz CPU clock) or 100 MHz (300MHZ CPU clock) by the Flash File System. The EMIF clock