Kane Industries C6713CPU - Manual (Page 16)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 16
2.4.1 User Programmable LED's (PLD)
These LED's are controlled by PLD registers (see chapter 3.10). They can be switched on and off
by application software to display certain events or states.
Examples for software controlled usage of the LED's are:
• displaying an error condition by the red LED
• checking software activity by toggling one of the LED each time the main loop is executed
• DSP load indicator, flashing the LED during interrupt handlers or calculations
Furthermore, the green LED can automatically be driven by other hardware activities:
• CE1 is active, PLD or UART is accessed
• Flash is accessed (default)
2.4.2 User Programmable LED (FPGA)
A yellow LED is directly connected to the FPGA. The function is defined by the respective FPGA
design or BSP and is described in the BSP documentation.
2.5 DSP peripherals
The TMS320C6713 DSP has a number peripheral interfaces integrated on the chip. These
interfaces are described briefly in this chapter. Hardware and programming details can be found in
the respective literature from Texas Instruments [6] to [9].
Some of the DSP peripheral interfaces share pins with others. Therefore, care must be taken when
using multiple peripherals to ensure that all interfaces are available at the same time.
2.5.1 Multichannel Audio Serial Ports (McASP)
The McASPs are serial ports, optimized for the needs of multi-channel audio applications. Two
McASP ports are available on the TMS320C6713. The McASP ports are described in [4] and [7] in
detail.
The signals of the McASP ports are shared with signals of other DSP peripherals like:
• McBSPs
• Timers
• GPIO 5 / EXT_INT5
• GPIO 4 / EXT_INT4
• Host Port Interface
At the C6713CPU board, the McASP0 port is available at micro-line
® connectors. Chapter 6.3
contains detailed tables of shared signals. Further information can also be found in [4].
By default, the McASP1 port is disabled by hardware and the Host Port Interface (HPI) is enabled
therefore. If McASP1 is needed for a certain application, a slight hardware reconfiguration on the
C6713CPU board is necessary. In this case please contact ORSYS. Further details about McASP1
configuration are also described in chapter 7.2.
2.5.2 External Memory Interface (EMIF)
The EMIF is the main on-board 32 bit bus-interface between the DSP and other components. It is
connected to:
• on-board memory (SDRAM, flash memory)
• on-board peripherals (PLD)
• FPGA
The EMIF can also be used to access off-board hardware by using an appropriate FPGA design.
This can either be a standard BSP from ORSYS, or a custom FPGA design.
The EMIF is mapped into the DSP's address space, separated into four areas called CE spaces: