Xilinx V2.1 - Manual (Page 101)

MATLAB I/O 101
Xilinx Blocks
NET "Dout<2>" FAST;
NET "Dout_valid" FAST;
•
Specify IOB Location Constraints : Checking this option allows IOB
location constraints to be specified.
•
IOB Pad Locations, e.g. {'Valid Bit', 'MSB', ...., 'LSB'} :
IOB pin locations can be specified as a cell array of strings in this edit box. The
locations are package-specific. For the above example, if a Virtex-E 2000 in a
FG680 package is used, the location constraints for the
Dout bus can be specified
in the dialog box as {'C33', 'B34', 'D33', 'B35'} . This is translated
into constraints in the . ucf file in the following way:
# Loc constraints
NET "Dout<0>" LOC = "B35";
NET "Dout<1>" LOC = "D33";
NET "Dout<2>" LOC = "B34";
NET "Dout_valid" LOC = "C33";
Other parameters used by this block are described in the Common Parameters section
of the previous chapter.
The Gateway Out block cannot be placed in an enabled subsystem in System
Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library
documentation) explanation for more details.
Quantization Error Blocks
Clear Quantization Error
The Clear Quantization Error block clears the quantization error tracking
mechanism on a trace. Inserting this block has no effect on the
computation other than the error analysis sections.
Quantization Error
The Xilinx Quantization Error block extracts the quantization error
from a fixed point signal. This error is tracked as the difference
between the expected value (exact to machine precision) and the actual
value of the fixed point signal. You may view the quantization error by
sending the output of the block into a display or scope.
Display
This is the Simulink Display block, linked into the Xilinx Blockset’s
MATLAB I/O section as a convenience. It is presented as output to
the Sample Time display (described next).
Sample Time
The Sample Time block reports the sample period of its input. It is meant
to be displayed using the Display block, above.