Xilinx V2.1 - Manual (Page 116)

116 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
The rows of the matrices correspond to the current state, and columns correspond to
the input value.
The next state logic and state register in this block are implemented with high speed
dedicated block RAM. The output logic is implemented using a distributed RAM
configured as a lookup table, and therefore has zero latency.
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-79: Mealy State Machine block parameters dialog box
The maximum number of states is limited by the depth of the distributed RAM. For
the Virtex family, the maximum number of states supported is 4K and for Virtex-II it is
64K.
Xilinx LogiCORE
This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE and
Version 5.0 of the Xilinx Distributed RAM LogiCORE.
The Core datasheet for the Single Port Block Memory may be found locally at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do
c\sp_block_mem.pdf
The Core datasheet for the Distributed Memory may be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\c_dist_mem_v5_0\
doc\dist_mem.pdf
Moore State Machine
The Xilinx Moore State Machine block implements a state machine
whose output depends only on the current state.