Xilinx V2.1 - Manual (Page 8)

8 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Chapter 1
Introduction
This chapter describes the basic concepts and tools of the System Generator v2.1.
This chapter contains the following sections.
•
Industry and Product Overview
•
System Generator
•
System Level Modeling with System Generator
•
The System Generator Design Flow
•
Arithmetic Data Types
•
Hardware Handshaking
•
Bit-true and Cycle-true Modeling
Industry and Product Overview
In recent years, field-programmable gate arrays (FPGAs) have become key
components in implementing high performance digital signal processing (DSP)
systems, especially in the areas of digital communications, networking, video, and
imaging. The logic fabric of today's FPGAs consists not only of look-up tables,
registers, multiplexers, distributed and block memory, but also dedicated circuitry for
fast adders, multipliers, and I/O processing (e.g., giga-bit I/O). The memory
bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP processor
running at clock rates two to ten times that of the FPGA. Coupled with a capability
for implementing highly parallel arithmetic architectures, this makes the FPGA
ideally suited for creating high-performance custom data path processors for tasks
such as digital filtering, fast Fourier transforms, and forward error correction.
For example, all major telecommunication providers have adopted FPGAs for high-
performance DSP out of necessity. A third-generation (3G) wireless base station
typically contains FPGAs and ASICs in addition to microprocessors and digital signal
processors (DSPs). The processors and DSPs, even when running at GHz clock rates,
are increasingly used for relatively low MIPs packet level processing, with the chip
and symbol rate processing being implemented in the FPGAs and ASICs. The fluidity
of emerging standards often makes FPGAs, which can be reprogrammed in the field,
better suited than ASICs.
Despite these characteristics, broader acceptance of FPGAs in the DSP community has
historically been hampered by several factors. First, there is a general lack of
familiarity with hardware design and especially, FPGAs. DSP engineers conversant
with programming in C or assembly language are often unfamiliar with digital design
using hardware description languages (HDLs) such as VHDL or Verilog.
Furthermore, although VHDL provides many high level abstractions and language