Xilinx V2.1 - Manual (Page 38)

38 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Mux
The Xilinx Mux block implements a multiplexer.
The block has one select input (type unsigned) and a user-
configurable number of data bus inputs, ranging from 2 to
32.
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-13: Mux block parameters dialog box
Parameters specific to the block are:
•
Number of Inputs : specifies the number of data bus inputs, from 2 to 32.
•
Use Placement Information for Core : when checked, the generated core
includes relative placement information. This usually results in a faster
implementation. The resulting floorplan is a single column with two bits per slice.
With this placement, large multiplexers may not fit into small Xilinx devices.
When unchecked, the core is generated as unplaced logic.
Other parameters used by this block are described in the Common Parameters section
of the previous chapter.
Xilinx LogiCORE
The block uses the Xilinx LogiCORE Bus Multiplexer V5.0. When the Generate Core
parameter is checked, the Use Placement Information for Core parameter provides the
option of generating the core as a Relationally Placed Macro (RPM) or as unplaced
logic.
The Core datasheet can be found on your local disk at: