Xilinx V2.1 - Manual (Page 42)

42 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Reinterpret
The Reinterpret block forces its output to a new type without any
regard for retaining the numerical value represented by the input. The
binary representation is passed through unchanged, so in hardware this
block consumes no resources. The number of bits in the output will
always be the same as the number of bits in the input.
The block allows for unsigned data to be reinterpreted as signed data, or, conversely,
for signed data to be reinterpreted as unsigned. It also allows for the reinterpretation
of the data’s scaling, through the repositioning of the binary point within the data.
The Xilinx Scale block provides an analagous capability.
An example of this block’s use is as follows: if the input type is 6 bits wide and signed,
with 2 fractional bits and the output type is forced to be unsigned with 0 fractional
bits, then an input of -2.0 (1110.00 in binary, two’s complement) would be translated
into an output of 56 (111000 in binary).
This block can be particularly useful in applications that combine it with the Xilinx
Slice block or the Xilinx Concat block. To illustrate the block’s use, consider the
following scenario:
Given two signals, one carrying signed data and the other carrying two unsigned
bits (a
UFix_2_0 ), we want to design a system that concatenates the two bits
from the second signal onto the tail (least significant bits) of the signed signal.
We can do so using two Reinterpret blocks and one Concat block. The first
Reinterpret block is used to force the signed input signal to be treated as an
unsigned value with its binary point at zero. The result is then fed through the
Concat block along with the other signal’s
UFix_2_0 . The Concat operation is
then followed by a second Reinterpret that forces the output of the Concat block
back into a signed interpretation with the binary point appropriately
repositioned.
Though three blocks are required in this construction, the hardware
implementation will be realized as simply a bus concatenation, which has no cost
in hardware.