Xilinx V2.1 - Manual (Page 14)

14 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Bit-True and Cycle-True Modeling
System Generator produces a hardware implementation that is bit and cycle true to
the system level simulation. We define the term bit and cycle true at the boundaries of
the design. The boundaries of a design in System Generator are specified by the
presence of Gateway In and Gateway Out blocks. These form interfaces between data
representation within System Generator and data types that can be examined and
manipulated in the standard Simulink environment. The gateways are translated into
ports in the implemented hardware design. The Gateway In blocks become input
ports to the design and the Gateway Out blocks become output ports.
In the Simulink simulation, Gateway in and Out blocks have data samples flowing
through at regular sample periods. The values flowing in provide the stimuli, and
those flowing out represent the response. In the generated hardware, if an identical
stimulus sequence is presented at the input ports (at clock events corresponding to the
input sample periods), then identical output sequences will be observed (here at clock
events corresponding to Simulink output events). The values presented to the
hardware input ports and produced by the output ports are bit vectors interpreted as
representing the fixed point values of the Simulink simulation. This correspondence
between Simulink and hardware results is guaranteed to hold regardless of the
particular input stimulus to the design or the positioning or number of Gateway Out
blocks.
Automatic Testbench Generation
For a black box instantiation, the design must provide both a Simulink model and an
implementation. System Generator cannot automatically provide the verification that
the two representations of the black box match. To assist the designer in verifying that
the system model simulated in Simulink mirrors the generated hardware circuit, a
VHDL test bench is automatically created during HDL code generation.
Test bench input stimuli are recorded by Gateway In blocks during Simulink
simulation. These blocks quantize double precision input date into a fixed point
representation. The fixed point values are saved to a data file and then used as input
stimuli during VHDL simulation.
Gateway Out blocks convert the fixed point representation into Simulink floating
point and define the output data ports of the HDL design. The signal connected to the
input of a Gateway In block is sampled at a given sample rate and is used as expected
data in the HDL simulation.
During HDL code generation, each Gateway In block is translated to a VHDL
component which reads the input stimuli. Gateway Out blocks are translated to
components that compare the VHDL results to the expected results. The comparisons
are performed at the blocks' sample rates. Only values which are tagged as valid by
the valid bit are compared.
The fixed point data type in Simulink is represented using a std_logic_vector in
VHDL. The position of the binary point, size of the container, and treatment of sign
are supplied to the VHDL as generic parameters. To ease the interpretation of fixed
point types in VHDL, the Gateway In and Out blocks convert the
std_logic_vector into a real number representation by using the generic
parameter information. A sequence of real numbers can then be viewed as an analog
waveform in an HDL simulator.