Xilinx V2.1 - Manual (Page 137)

Files automatically created by System Generator 137
System Generator Software Features
Files automatically created by System Generator
When a System Generator project is created, the software produces design VHDL and
cores from the Xilinx CORE Generator. In addition, many other project files are
created. Following is a description of the files you can expect to find in your System
Generator generated project directory. For this example, we will assume your top-
level project name is
my_project , and that this project contains one multiplier core:
•
my_project.vhd - the top level VHDL file for your project. There are additional
VHDL files included when your design has more hierarchy.
•
my_project_xlmult_core1 - files associated with the generated multiplier
core, such as the behavioral simulation models and EDIF file.
•
corework - subdirectory containing the CORE Generator log file.
•
my_project.ucf - generated constraints file. Buses in this file are denoted with
angle brackets, as described in the previous Constraints Files section. This file
should be used with XST from within Project Navigator and with Synplify and
Leonardo Spectrum when using the project files produced by System Generator.
•
my_project_paren.ucf - use this constraints file if you are using the Synplify
or Leonardo synthesis compilers through Xilinx ISE 4.1i Project Navigator. In this
file, buses are denoted with parentheses.
•
my_project.npl - project file for opening the design in Xilinx ISE 4.1i Project
Navigator, using the XST synthesis compiler and ModelSim simulator.
•
my_project_testbench.vhd - the top level VHDL testbench file, associated
with the top level VHDL source file in the project.
•
my_project_<gateways>.dat - stimulus files for inputs to testbenches, or
predicted outputs of testbenches. The .dat files are generated by Simulink
simulation and saved for running in Xilinx testbenches to verify design behavior.
In this example,
<gateways> refers to the names of the Xilinx gateway blocks,
which collect and save the data.
•
vhdlFiles - a list of VHDL files, and their dependency order, needed for
synthesis projects. System Generator’s Perl scripts read from this file when
creating project files.
•
globals - a file containing the characteristics of the design needed by
downstream software tools in order to synthesize and implement.
•
my_project_synplicity.prj - a project file for running this design in
Synplify (synthesis tools from Synplicity).
•
edif_bit_format.sdc - a Synplify constraints file used to set the bus format to
angle brackets. This file is used by the my_project_synplicity.prj file.
•
my_project_leon.tcl - a project file for running this design in Leonardo
Spectrum (synthesis tools from Exemplar).
•
my_project_xst.prj - a project file for running this design in XST (Xilinx
Synthesis Technology).
•
pn_behavioral.do, pn_posttranslate.do, pn_postmap.do,
pn_postpar.do - compilation and simulation do files for running this design
through simulation at different stages. These 4 files are associated with ModelSim
simulation through the Xilinx ISE 4.1i Project Navigator.
•
vcom.do, vsim.do - default behavioral simulation files for use with ModelSim.