Xilinx V2.1 - Manual (Page 19)

Common Options in Block Parameters Dialog Box 19
Xilinx Blockset Overview
Xilinx LogiCORE

Versions
The Xilinx LogiCORE

blocks (indicating the version numbers being supported by
the System Generator) used in Xilinx System Generator v2.1 are listed below.
Common Options in Block Parameters Dialog Box
Each Xilinx block has several configurable parameters, seen in the block parameters
dialog box. Many of these parameters are specific to that particular block. Those block
Xilinx Block Xilinx LogiCORE Version
Accumulator ACCUMULATOR V5.0
Addressable Shift
Register RAM_SHIFT V5.0
Adder/Subtractor ADDSUB V5.0
CIC CIC V1.0
Counter BINARY_COUNTER V5.0
Constant Multiplier MULT_GEN V4.0
Convolutional
Encoder CONVOLUTION V1.0
DDS DDS V4.0
Dual Port Ram MEM_DP_BLOCK V3.2
FIFO SYNC_FIFO V3.0
FFT FFT and MEM_DP_BLOCK V1.0 (Virtex, Spartan-II),
V2.0 (Virtex-II)
V3.2 (MEM_DP_BLOCK)
FIR Filter DA_FIR V6.0
Interleaver/
Deinterleaver INTERLEAVER V1.1
Inverter GATE_BUS V5.0
Logical GATE_BUS V5.0
Multiplier (mult) MULT_GEN V4.0
Mutiplexer (mux) BUS_MUX V5.0
Negate TWOS_COMP V5.0
Relational COMPARE V5.0
RS Decoder RS_DECODER V2.0
RS Encoder RS_ENCODER V2.0
Sine Cosine SIN_COS V3.0
Single Port RAM MEM_SP_BLOCK and
DIST_MEM
V3.2(BRAM), V5.0 (dist.)
State Machines MEM_SP_BLOCK and
DIST_MEM
V3.2(BRAM), V5.0 (dist.)
ROM MEM_SP_BLOCK and
DIST_MEM
V3.2 (BRAM), V5.0 (dist.)
Viterbi Decoder VITERBI V1.0