Document Outline

• Features
  • Reference Documents
  • Product Description
  • AT8xC5122 Block Diagram
  • AT83C5123 Block Diagram
• Pinout
  • High Pin Count Package Description
    • AT8xC5122 version
    • AT89C5122DS version
  • Low Pin Count Package Description
    • AT8xC5122 and AT83C5123 versions
    • AT83C5123 version
  • Pin Description
• Typical Applications
  • Recommended External components
  • USB Keyboard with Smart Card Reader Using the AT8xC5122 and AT89C5122DS Versions
  • USB Smart Card Reader Using the AT83C5123 Version
• Memory Organization
  • Program Memory Managament
  • Data Memory Managament
    • RAM Achitecture
    • XRAM Achitecture
  • Dual Data Pointer Register (DDPTR)
    • Assembly Language
  • Registers
  • AT8xC5122’s CRAM and E2PROM Versions
    • Using CRAM Memory
  • AT8xC5122’s ROM Version
    • Security Level
  • AT83C5123 Version
• Special Function Registers (SFR’s)
  • Introduction
  • AT8xC5122 Version
  • AT83C5123 Version
  • SFR’s Description
• Clock Controller
  • On-Chip Oscillator
    • Quartz Specification
  • Phase Lock Loop (PLL)
    • PLL Description
    • PLL Programming
  • Clock Tree Architecture
    • CPU and Peripheral Clocks
      • X1 and X2 Modes
      • Table 1. X1 and X2 Mode Selection
      • Use of PLL Clock
    • SCIB Clock
    • Alternate Card Clock
    • DC/DC Converter Clock
    • USB Interface Clock
  • Registers
• I/O Port Definition
  • Ports vs Packages
  • Port 0
  • Port 1
  • Port 2
  • Port 3
  • Port 4
  • Port 5
  • Port Configuration
    • Standard I/O P0
    • Quasi Bi-directional Port
    • Push-pull Output Configuration
    • Input with Medium or Weak Pull-up Configuration
    • Input with Weak Pull-down Configuration
    • Low Speed Output Configuration
    • LED Source Current
  • Registers
• Smart Card Interface Block (SCIB)
  • Block Diagram
  • Definitions
    • Terminal and ICC
    • ETU
    • T=0
    • T=1
    • Activation: Cold Reset
    • Activation: Warm Reset
    • De-Activation
    • ATR
    • F and D
    • Guard Time
    • Extra Guard Time
    • Block Guard Time
    • Work Waiting Time (WWT)
    • Character Waiting Time (CWT)
    • Block Waiting Time (BWT)
    • Waiting Time Extention (WTX)
    • Parity error in T=0 protocol
  • Functional Description
    • Barrel Shifter
    • SCART FSM
    • ETU Counter
    • Guard Time Counter
    • Block Guard Time Counter
    • Waiting Time (WT) Counter
    • Power-on and Power-off FSM
    • Interrupt Generator
  • Additional Features
    • Clock
    • Card Presence Input
    • Transmit / Receive Buffer
    • SCIB Reset
  • Alternate Card
  • Registers
  • DC/DC Converter
    • Configuration
    • Initialization Procedure
    • Procedure for CVcc =< 3 volts
    • Procedure for CVcc = 5volts
    • Monitoring Procedure
    • DC/DC Converter register
• USB Controller
  • USB Mass Storage Classes
    • USB Mass Storage Class CBI Transport
    • USB Mass Storage Class Bulk- Only Transport
  • USB Device Firmware Upgrade (DFU)
  • Description
    • Serial Interface Engine (SIE)
    • Function Interface Unit (UFI)
  • Configuration
    • General Configuration
    • Endpoint Configuration
  • Read/Write Data FIFO
    • Read Data FIFO
    • Write Data FIFO
  • Bulk / Interrupt Transactions
    • Bulk/Interrupt OUT Transactions in Standard Mode
    • Bulk/Interrupt OUT Transactions in Ping-Pong Mode (Endpoints 6)
    • Bulk/Interrupt IN Transactions In Standard Mode
    • Bulk/Interrupt IN Transactions in Ping-Pong Mode
  • Control Transactions
    • Setup Stage
    • Data Stage: Control Endpoint Direction
    • Status Stage
  • Isochronous Transactions
    • Isochronous OUT Transactions in Standard Mode
    • Isochronous OUT Transactions in Ping-pong Mode
    • Isochronous IN Transactions in Standard Mode
    • Isochronous IN Transactions in Ping-Pong Mode
  • Miscellaneous
    • USB Reset
    • STALL Handshake
    • Start of Frame Detection
    • Frame Number
    • Data Toggle Bit
    • NAK Handshakes
  • Suspend/Resume Management
    • Suspend
    • Resume
    • Upstream Resume
  • Detach Simulation
  • USB Interrupt System
    • Interrupt System Priorities
    • Interrupt Control System
  • Registers
• Serial I/O Port
  • Framing Error Detection
  • Automatic Address Recognition
    • Given Address
    • Broadcast Address
    • Reset Addresses
    • Timer 1
    • Internal Baud Rate Generator
    • Synchronous Mode (Mode 0)
    • Transmission (Mode 0)
    • Reception (Mode 0)
    • Baud Rate Selection (Mode 0)
  • Asynchronous Modes (Modes 1, 2 and 3)
    • Mode 1
  • Modes 2 and 3
    • Transmission (Modes 1, 2 and 3)
    • Reception (Modes 1, 2 and 3)
    • Framing Error Detection (Modes 1, 2 and 3)
    • Baud Rate Selection (Modes 1 and 3)
    • Baud Rate Selection (Mode 2)
  • Registers
• Serial Port Interface (SPI)
  • Features
  • Signal Description
    • Master Output Slave Input (MOSI)
    • Master Input Slave Output (MISO)
    • SPI Serial Clock (SCK)
    • Slave Select (SS)
    • Baud Rate
  • Functional Description
    • Operating Modes
      • Master Mode
      • Slave Mode
    • Transmission Formats
    • Error Conditions
      • Mode Fault (MODF)
      • Write Collision (WCOL)
      • Overrun Condition
      • SS Error Flag ( SSERR )
    • Interrupts
    • Registers
      • Serial Peripheral Control Register (SPCON)
      • Serial Peripheral Status Register (SPSTA)
      • Serial Peripheral DATa Register (SPDAT)
• Timers/Counters
  • Timer/Counter Operations
  • Timer 0
    • Mode 0 (13-bit Timer)
    • Mode 1 (16-bit Timer)
    • Mode 2 (8-bit Timer with Auto- Reload)
    • Mode 3 (Two 8-bit Timers)
  • Timer 1
    • Mode 0 (13-bit Timer)
    • Mode 1 (16-bit Timer)
    • Mode 2 (8-bit Timer with Auto- Reload)
    • Mode 3 (Halt)
  • Registers
• Keyboard Interface
  • Introduction
  • Description
    • Interrupt
    • Power Reduction Mode
  • Registers
• Interrupt System
  • Introduction
  • Interrupt System Description
    • INT1 Interrupt Vector
    • INT1 Input
    • RXD Input
    • CPRES Input
  • Registers
  • Interrupt Sources and Vectors
• Microcontroller Reset
  • Introduction
  • Power On Reset (POR)
  • Power Fail Detector (PFD)
  • Reset pin
    • Long Reset
    • Reset Controlled by the User
    • Reset Controlled by an External Superviser Device
  • Watchdog Timer
• Power Management
  • Idle Mode
  • Power Down Mode
  • Reduced EMI Mode
  • USB Interface
    • Suspend
    • Resume
  • Smart Card Interface
    • Entering in Power-down Mode
    • Exiting from Power-down Mode
  • Keyboard Interface
    • Entering in Power-down Mode
    • Exiting from Power-down Mode
  • Watchdog Timer during Power-down and Idle Mode
  • Registers
• Electrical Characteristics
  • Absolute Maximum Ratings
  • DC Parameters
    • ICC Current Test Conditions
  • LED’s
  • Smart Card Interface
  • USB Interface
  • AC Parameters
    • Explanation of the AC Symbols
    • External Program Memory Characteristics
    • External Program Memory Read Cycle
    • External Data Memory Characteristics
    • External Data Memory Write Cycle
    • External Data Memory Read Cycle
    • Serial Port Timing - Shift Register Mode
    • Shift Register Timing Waveform
    • External Clock Drive Characteristics (XTAL1)
    • External Clock Drive Waveforms
    • AC Testing Input/Output Waveforms
  • Float Waveforms
    • Clock Waveforms
    • USB Interface
• Packaging Information
  • Ordering Information
  • Mechanical Dimensions
    • PLCC28 Package
    • VQFP64 Package
    • PLCC68 Package
    • VQFP32 Package
    • QFN32 Package
    • QFN64 Package
• Datasheet Revision History
  • Changes from 4202A to 4202B
  • Changes from 4202B to 4202C
  • Changes from 4202C to 4202D
  • Changes from 4202D to 4202E
• Table of Contents