ARM VERSION 1.2 - Manual (Page 117)

ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-7
4.2.1 LDR and STR, words and unsigned bytes
Load register and store register, 32-bit word or 8-bit unsigned byte. Byte loads are
zero-extended to 32 bits.
Syntax
Both LDR and STR have four possible forms:
• zero offset
• pre-indexed offset
• program-relative
• post-indexed offset.
The syntax of the four forms, in the same order, are:
op{cond}{B}{T} Rd, [Rn]
op{cond}{B} Rd, [Rn, FlexOffset]{!}
op{cond}{B} Rd, label
op{cond}{B}{T} Rd, [Rn], FlexOffset
where:
op is either LDR (Load Register) or STR (Store Register).
cond is an optional condition code (see Conditional execution on page 4-4).
B
is an optional suffix. If B is present, the least significant byte of Rd is
transferred. If op is LDR , the other bytes of Rd are cleared.
Otherwise, a 32-bit word is transferred.
T is an optional suffix. If T is present, the memory system treats the access
as though the processor was in User mode, even if it is in a privileged
mode (see Processor mode on page 2-4).
T has no effect in User mode.
You cannot use T with a pre-indexed offset.
Rd is the ARM register to load or save.
Rn is the register on which the memory address is based.
Rn must not be the same as Rd , if the instruction:
• is pre-indexed with writeback (the ! suffix)
• is post-indexed
• uses the T suffix.