ARM VERSION 1.2 User Manual
Page 129
ARM Instruction Reference
ARM DUI 0068B
Copyright © 2000, 2001 ARM Limited. All rights reserved.
4-19
Non word-aligned addresses
These instructions ignore bits [1:0] of the address. (On a system with a system
coprocessor, if alignment checking is enabled, nonzero values in these bits cause an
alignment exception.)
Loading to r15
A load to r15 (the program counter) causes a branch to the instruction at the address
loaded. In T variants of ARM architecture v5 and above, a load to r15 causes a change
to executing Thumb instructions if bit 0 of the value loaded is set.
Loading or storing the base register, with writeback
If
Rn
is in
reglist
, and writeback is specified with the
!
suffix:
•
if
op
is
STM
and
Rn
is the lowest-numbered register in
reglist
, the initial value of
Rn
is stored
•
otherwise, the loaded or stored value of
Rn
is unpredictable.
Architectures
These instructions are available in all versions of the ARM architecture.
In T variants of ARM architecture v5 and above, a load to r15 causes a change to
executing Thumb instructions if bit 0 of the value loaded is set.
Examples
LDMIA r8,{r0,r2,r9}
STMDB r1!,{r3-r6,r11,r12}
STMFD r13!,{r0,r4-r7,LR} ; Push registers including the
; stack pointer
LDMFD r13!,{r0,r4-r7,PC} ; Pop the same registers and
; return from subroutine
Incorrect examples
STMIA r5!,{r5,r4,r9} ; value stored for r5 unpredictable
LDMDA r2, {} ; must be at least one register in list