ARM VERSION 1.2 - Manual (Page 20)

Writing ARM and Thumb Assembly Language
2-8 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
2.2.6 ARM instruction capabilities
The following general points apply to ARM instructions:
• Conditional execution
• Register access
• Access to the inline barrel shifter.
Conditional execution
Almost all ARM instructions can be executed conditionally on the value of the ALU
status flags in the CPSR. You do not need to use branches to skip conditional
instructions, although it can be better to do so when a series of instructions depend on
the same condition.
You can specify whether a data processing instruction sets the state of these flags or not.
You can use the flags set by one instruction to control execution of other instructions
even if there are many instructions in between.
Refer to Conditional execution on page 2-20 for a detailed description.
Register access
In ARM state, all instructions can access r0 to r14, and most also allow access to r15
(pc). The
MRS and MSR instructions can move the contents of the CPSR and SPSRs to a
general-purpose register, where they can be manipulated by normal data processing
operations. Refer to MRS on page 4-73 and MSR on page 4-74 for more information.
Access to the inline barrel shifter
The ARM arithmetic logic unit has a 32-bit barrel shifter that is capable of shift and
rotate operations. The second operand to all ARM data-processing and single register
data-transfer instructions can be shifted, before the data-processing or data-transfer is
executed, as part of the instruction. This supports, but is not limited to:
• scaled addressing
• multiplication by a constant
• constructing constants.
Refer to Loading constants into registers on page 2-25 for more information on using
the barrel-shifter to generate constants.