ARM VERSION 1.2 - Manual (Page 265)

Vector Floating-point Programming
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 6-27
6.7.9 FMAC, FNMAC, FMSC, and FNMSC
Floating-point multiply-accumulate, negate-multiply-accumulate, multiply-subtract
and negate-multiply-subtract. These instructions can be scalar, vector, or mixed (see
Vector and scalar operations on page 6-7).
Syntax
<op><precision>{cond} Fd, Fn, Fm
where:
<op>
must be one of FMAC , FNMAC , FMSC , or FNMSC .
<precision>
must be either S for single-precision, or D for double-precision.
cond is an optional condition code (see VFP and condition codes on page 6-8).
Fd is the VFP register for the result.
Fn is the VFP register holding the first operand.
Fm is the VFP register holding the second operand.
The precision of Fd , Fn and Fm must match the precision specified in <precision> .
Usage
The FMAC instruction calculates Fd + Fn * Fm and places the result in Fd .
The FNMAC instruction calculates Fd – Fn * Fm and places the result in Fd .
The FMSC instruction calculates – Fd + Fn * Fm and places the result in Fd .
The FNMSC instruction calculates – Fd – Fn * Fm and places the result in Fd .
Exceptions
These operations can produce Invalid Operation, Overflow, Underflow, or Inexact
exceptions.
Examples
FMACD d8, d0, d8
FMACS s20, s24, s28