ARM VERSION 1.2 - Manual (Page 201)

Thumb Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 5-7
5.1.2 LDR and STR, register offset
Load Register and Store Register. Address in memory specified as a register-based
offset from a value in a register.
Syntax
op Rd, [Rn, Rm]
where:
op is one of the following:
LDR Load register, 4-byte word
STR Store register, 4-byte word
LDRH Load register, 2-byte unsigned halfword
LDRSH Load register, 2-byte signed halfword
STRH Store register, 2-byte halfword
LDRB Load register, unsigned byte
LDRSB Load register, signed byte
STRB Store register, byte.
Note
There is no distinction between signed and unsigned store instructions.
Rd is the register to be loaded or stored. Rd must be in the range r0 - r7 .
Rn is the register containing the base address. Rn must be in the range r0 - r7 .
Rm is the register containing the offset. Rm must be in the range r0 - r7 .
Usage
STR instructions store a word, halfword, or byte from Rd to memory.
LDR instructions load a word, halfword, or byte from memory to Rd .
The address is found by adding the offset to the base address from Rn .
Register offset halfword and byte loads can be signed or unsigned. The data is loaded
into the least significant word or byte of
Rd , and the rest of Rd is filled with zeroes for an
unsigned load, or with copies of the sign bit for a signed load.