ARM VERSION 1.2 - Manual (Page 224)

Thumb Instruction Reference
5-30 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
5.3.5 TST
Test bits.
Syntax
TST Rn, Rm
where:
Rn is the register containing the first operand.
Rm is the register containing the second operand.
Usage
This instruction performs a bitwise logical AND operation on the values in Rm and Rn . It
updates the condition flags, but does not place a result in a register.
Restrictions
Rn and Rm must be in the range r0 - r7 .
Condition flags
This instruction updates the N and Z flags according to the result. The C and V flags are
unaffected.
Architectures
This instruction is available in all T variants of the ARM architecture.
Example
TST r2,r4