ARM VERSION 1.2 User Manual
Page 136
ARM Instruction Reference
4-26
Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM DUI 0068B
Figure 4-2 RRX
The carry flag
The carry flag is updated to the last bit shifted out of
Rm
, if the instruction is any one of
the following:
•
MOV
,
MVN
,
AND
,
ORR
,
EOR
or
BIC
, if you use the
S
suffix
•
TEQ
or
TST
, for which no
S
suffix is required.
Instruction substitution
Certain pairs of instructions (
ADD
and
SUB
,
ADC
and
SBC
,
AND
and
BIC
,
MOV
and
MVN
,
CMP
and
CMN
) are equivalent except for the negation or logical inversion of
immed_8r
.
If a value of
immed_8r
cannot be expressed as a rotated 8-bit pattern, but its logical
inverse or negation could be, the assembler substitutes the other instruction of the pair
and inverts or negates
immed_8r
.
Be aware of this when comparing disassembly listings with source code.
Examples
ADD r3,r7,#1020 ; immed_8r. 1020 is 0xFF rotated right by 30 bits.
AND r0,r5,r2 ; r2 contains the data for Operand2.
SUB r11,r12,r3,ASR #5 ; Operand2 is the contents of r3 divided by 32.
MOVS r4,r4, LSR #32 ; Updates the C flag to r4 bit 31. Clears r4 to 0.
Incorrect examples
ADD r3,r7,#1023 ; 1023 (0x3FF) is not a rotated 8-bit pattern.
SUB r11,r12,r3,LSL #32 ; #32 is out of range for LSL.
MOVS r4,r4,RRX #3 ; Do not specify a shift amount for RRX. RRX is
; always a one-bit shift.
31 30
1 0
Carry
Flag
...
...