ARM VERSION 1.2 User Manual
Page 264
Vector Floating-point Programming
6-26
Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM DUI 0068B
Usage
The
FLDM
instruction loads several consecutive floating-point registers from memory.
The
FSTM
instruction saves the contents of several consecutive floating-point registers to
memory.
If
<precision>
is specified as
D
,
VFPregisters
must be a list of double-precision registers,
and two words are transferred for each register in the list.
If
<precision>
is specified as
S
,
VFPregisters
must be a list of single-precision registers,
and one word is transferred for each register in the list.
Unspecified precision
If
<precision>
is specified as
X
,
VFPregisters
must be specified as double-precision
registers. However, any or all of the specified double-precision registers can actually
contain two single-precision values or integers.
The number of words transferred might be 2n or (2n + 1), where n is the number of
double-precision registers in the list. This is implementation dependent. However, if
writeback is specified,
Rn
is always adjusted by (2n + 1) words.
You must only use unspecified-precision loads and saves in matched pairs, to save and
restore data. The format of the saved data is implementation-dependent.
Examples
FLDMIAS r2, {s1-s5}
FSTMFDD r13!, {d3-d6}
FSTMIAS r0!, {s31}
The following instructions are equivalent:
FLDMIAS r7, {s3-s7}
FLDMIAS r7, {s3,s4,s5,s6,s7}
The following instructions must always be used as a matching pair:
FSTMFDX r13!, {d0-d3}
FLDMFDX r13!, {d0-d3}
The following instruction is illegal, as the registers in the list are not consecutive:
FLDMIAD r13!, {d0,d2,d3}