2 fadd and fsub – ARM VERSION 1.2 User Manual
Page 256
Vector Floating-point Programming
6-18
Copyright © 2000, 2001 ARM Limited. All rights reserved.
ARM DUI 0068B
6.7.2
FADD and FSUB
Floating-point add and subtract.
FADD
and
FSUB
can be scalar, vector, or mixed (see Vector and scalar operations on
Syntax
FADD<precision>{cond} Fd, Fn, Fm
FSUB<precision>{cond} Fd, Fn, Fm
where:
<precision>
must be either
S
for single-precision, or
D
for double-precision.
cond
is an optional condition code (see VFP and condition codes on page 6-8).
Fd
is the VFP register for the result.
Fn
is the VFP register holding the first operand.
Fm
is the VFP register holding the second operand.
The precision of
Fd
,
Fn
and
Fm
must match the precision specified in
<precision>
.
Usage
The
FADD
instruction adds the values in
Fn
and
Fm
and places the result in
Fd
.
The
FSUB
instruction subtracts the value in
Fm
from the value in
Fn
and places the result
in
Fd
.
Exceptions
FADD
and
FSUB
instructions can produce Invalid Operation, Overflow, or Inexact
exceptions.
Examples
FSUBSEQ s2, s4, s17
FADDDGT d4, d0, d12
FSUBD d0, d0, d12