ARM VERSION 1.2 - Manual (Page 16)

Writing ARM and Thumb Assembly Language
2-4 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
2.2.3 Processor mode
ARM processors support up to seven processor modes, depending on the architecture
version. These are:
• User
• FIQ - Fast Interrupt Request
• IRQ - Interrupt Request
• Supervisor
• Abort
• Undefined
• System (ARM architecture v4 and above).
All modes except User mode are referred to as privileged modes.
Applications that require task protection usually execute in User mode. Some
embedded applications might run entirely in Supervisor or System modes.
Modes other than User mode are entered to service exceptions, or to access privileged
resources. Refer to the Handling Processor Exceptions chapter in ADS Developer
Guide, and ARM Architecture Reference Manual for more information.
2.2.4 Registers
ARM processors have 37 registers. The registers are arranged in partially overlapping
banks. There is a different register bank for each processor mode. The banked registers
give rapid context switching for dealing with processor exceptions and privileged
operations. Refer to ARM Architecture Reference Manual for a detailed description of
how registers are banked.
The following registers are available in ARM architecture v3 and above:
• 30 general-purpose, 32-bit registers
• The program counter (pc) on page 2-5
• The Current Program Status Register (CPSR) on page 2-5
• Five Saved Program Status Registers (SPSRs) on page 2-5.
30 general-purpose, 32-bit registers
Fifteen general-purpose registers are visible at any one time, depending on the current
processor mode, as r0, r1, ... ,r13, r14.
By convention, r13 is used as a stack pointer (sp) in ARM assembly language. The C
and C++ compilers always use r13 as the stack pointer.