Fluke 900 - Manual (Page 21)

FLUKE 900 SERVICE MANUAL Theory of Operation
8 .
9.
10
.
11.
Diftest Buffers
This circuit uses one of two possible resistor values (Hi or Lo) to determine
whether the RDBUS can drive and therefore whether the pin is an output The
final output indicates the discrepancy between RDBUS and EBUS/SYNCBUS. It
may be foimd at the outputs of the exclusive OR gates on pages 8,9,10,11.
Self Test Latch
The shift register latch used to inject patterns onto the RDBUS during power-on
verification in earlier revison boards is incorporated into the Logic Cell Array at
U105, near the ZDF socket of the H3 Board. This is shown as circirit block 17 on the
block diagram. If a RD is inserted during the power-on test an t^arent failure will
result
RD Supply Relays
Certain ZIF socket pins are cormected to VCC or Gnd by closure of the relays
shown on page 7. The shift registers U155 and U102 control their selection.
Pin Dis Latch
These shift register latches can override the fault indication output from the Diftest
circuit to ignore a fault on a pin. They are shown on pages 8, 9, 10, 11, as U180,
U134, U89, U40.
FFCLK Line
The CPU can simulate a fault by asserting this line which is ORed with the pin fault
lines to produce FLTS, the master fault indicator (page 11, A-10). Shift register
U67 (page 3) provides data to a DAC which provides the FMASK reference
voltage used in the framing circuit. The charging of precision capacitors to this
voltage
establishes an FMASK value. Note that ttie 74ALS09s driving the
capacitors are specially prescreened to be uniform.
Mon Mux
The latches at U198, U153, U112, U64 hold the individual pin faults. The PALs
driving them are also latches which accumulate faults for 40 ns after the first line
fails but no further. In this way, the results are frozen in a window around the first
fail for later reading by the CPU over the Mon Bus. When no faults are present,
the signal M/F selects U164, U122, U76, U43 (pages 8, 9, 10, 11) to route the
EBUS onto the MONBUS.
Freq Circuit
The 8536 CIO at U27 (page 4) controls the multiplexing and measurement of
signal frequency among the 29 channels (28 pins plus 1 external). Port A is
configured as output and used to drive the muxes at U55, U66, U124, U141. Port B
drives the FREQ PAL except for PBS which is an input flagging the occurrence of
Gate. Port C is an input to read the frequency count.
Trig Buf
These buffers U191, U154, U98, U81 on page 2 enable the EBUS to the trigger
comparator when TBEN signal is active.
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