Comtrol eCos - Manual (Page 12)

III. The eCos Hardware Abstraction Layer (HAL) .......................................................................................... 169
6. Introduction .............................................................................................................................................. 171
7. Architecture, Variant and Platform .......................................................................................................... 173
8. General principles .................................................................................................................................... 175
9. HAL Interfaces ......................................................................................................................................... 177
Base Definitions .................................................................................................................................. 177
Byte order .................................................................................................................................. 177
Label Translation ...................................................................................................................... 177
Base types ................................................................................................................................. 177
Atomic types ............................................................................................................................. 178
Architecture Characterization ............................................................................................................. 178
Register Save Format ................................................................................................................ 178
Thread Context Initialization .................................................................................................... 178
Thread Context Switching ........................................................................................................ 179
Bit indexing ............................................................................................................................... 180
Idle thread activity .................................................................................................................... 180
Reorder barrier .......................................................................................................................... 180
Breakpoint support .................................................................................................................... 180
GDB support ............................................................................................................................. 181
Setjmp and longjmp support ..................................................................................................... 181
Stack Sizes ................................................................................................................................ 181
Address Translation .................................................................................................................. 182
Global Pointer ........................................................................................................................... 182
Interrupt Handling .............................................................................................................................. 182
Vector numbers ......................................................................................................................... 182
Interrupt state control ................................................................................................................ 183
ISR and VSR management ....................................................................................................... 184
Interrupt controller management ............................................................................................... 184
Clock control ............................................................................................................................. 186
Microsecond Delay ................................................................................................................... 186
HAL I/O .............................................................................................................................................. 186
Register address ........................................................................................................................ 186
Register read ............................................................................................................................. 187
Register write ............................................................................................................................ 187
Cache Control ..................................................................................................................................... 187
Cache Dimensions .................................................................................................................... 188
Global Cache Control ............................................................................................................... 189
Cache Line Control ................................................................................................................... 190
Linker Scripts ..................................................................................................................................... 191
Diagnostic Support ............................................................................................................................. 192
SMP Support ...................................................................................................................................... 192
Target Hardware Limitations .................................................................................................... 192
HAL Support ............................................................................................................................. 193
CPU Control .................................................................................................................... 193
Test-and-set Support ........................................................................................................ 194
Spinlocks ......................................................................................................................... 194
Scheduler Lock ................................................................................................................ 195
Interrupt Routing ............................................................................................................. 196
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