Comtrol eCos - Manual (Page 304)

Chapter 10. Exception Handling
PowerPC
A separate trampoline is contained in each of the vector locations. This code saves a few work registers away
to the special purposes registers available, loads the exception number into a register and then uses that to
index the VSR table and jump to the VSR. The VSR is entered with some registers move to the SPRs, and
one of the data register containing the number of the vector taken.
MIPS
A single trampoline routine attached to the common vector reads the exception code out of the cause register
and uses that value to index the VSR table and jump to the VSR. The trampoline uses the two registers defined
in the ABI for kernel use to do this, one of these will contain the exception vector number for the VSR.
IA32
There is a separate 3 or 4 instruction trampoline pointed to by each active IDT table entry. The trampoline for
exceptions that also have an error code pop it from the stack and put it into a memory location. Trampolines
for non-error-code exceptions just zero the memory location. Then all trampolines push an interrupt/exception
number onto the stack, and take an indirect jump through a precalculated offset in the VSR table. This is all
done without saving any registers, using memory-only operations. The VSR is entered with the vector number
pushed onto the stack on top of the standard hardware saved state.
ARM
The trampoline consists solely of the single instruction at the exception entry point. This is an indirect jump
via a location 32 bytes higher in memory. These locations, from 0x20 up, form the VSR table. Since each
VSR is entered in a different CPU mode ( SVC,UNDEF,ABORT,IRQ or FIQ ) there has to be a different VSR
for each exception that knows how to save the CPU state correctly.
Default Synchronous Exception Handling
Most synchronous exception VSR table entries will point to a default exception VSR which is responsible for
handling all exceptions in a generic manner. The default VSR simply saves the CPU state, makes any adjustments
to the CPU state that is necessary, and calls
cyg_hal_exception_handler() .
cyg_hal_exception_handler() needs to pass the exception on to some handling code. There are two basic
destinations: enter GDB or pass the exception up to eCos. Exactly which destination is taken depends on the
configuration. When the GDB stubs are included then the exception is passed to them, otherwise it is passed to
eCos.
If an eCos application has been loaded by RedBoot then the VSR table entries will all point into RedBoot’s ex-
ception VSR, and will therefore enter GDB if an exception occurs. If the eCos application wants to handle an
exception itself, it needs to replace the the VSR table entry with one pointing to its own VSR. It can do this with
the
HAL_VSR_SET_TO_ECOS_HANDLER() macro.
Default Interrupt Handling
Most asynchronous external interrupt vectors will point to a default interrupt VSR which decodes the actual inter-
rupt being delivered from the interrupt controller and invokes the appropriate ISR.
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