Comtrol eCos User Manual
Page 231
Chapter 5. Installation and Testing
// *** XINT7 interrupts ***
// I2C interrupts
#define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
#define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL
14
#define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR
15
#define CYGNUM_HAL_INTERRUPT_I2C_STOP
16
#define CYGNUM_HAL_INTERRUPT_I2C_LOSS
17
#define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS
18
// Messaging Unit interrupts
#define CYGNUM_HAL_INTERRUPT_MESSAGE_0
19
#define CYGNUM_HAL_INTERRUPT_MESSAGE_1
20
#define CYGNUM_HAL_INTERRUPT_DOORBELL
21
#define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL
22
#define CYGNUM_HAL_INTERRUPT_QUEUE_POST
23
#define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24
#define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER
25
// PCI Address Translation Unit
#define CYGNUM_HAL_INTERRUPT_BIST
26
// *** External board interrupts (XINT3) ***
#define CYGNUM_HAL_INTERRUPT_TIMER
27 // external timer
#define CYGNUM_HAL_INTERRUPT_ETHERNET
28 // onboard enet
#define CYGNUM_HAL_INTERRUPT_SERIAL_A
29 // 16x50 uart A
#define CYGNUM_HAL_INTERRUPT_SERIAL_B
30 // 16x50 uart B
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTD
31 // secondary PCI INTD
// The hardware doesn’t (yet?) provide masking or status for these
// even though they can trigger cpu interrupts. ISRs will need to
// poll the device to see if the device actually triggered the
// interrupt.
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTC
32 // secondary PCI INTC
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTB
33 // secondary PCI INTB
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTA
34 // secondary PCI INTA
// *** NMI Interrupts go to FIQ ***
#define CYGNUM_HAL_INTERRUPT_MCU_ERR
35
#define CYGNUM_HAL_INTERRUPT_PATU_ERR
36
#define CYGNUM_HAL_INTERRUPT_SATU_ERR
37
#define CYGNUM_HAL_INTERRUPT_PBDG_ERR
38
#define CYGNUM_HAL_INTERRUPT_SBDG_ERR
39
#define CYGNUM_HAL_INTERRUPT_DMA0_ERR
40
#define CYGNUM_HAL_INTERRUPT_DMA1_ERR
41
#define CYGNUM_HAL_INTERRUPT_DMA2_ERR
42
#define CYGNUM_HAL_INTERRUPT_MU_ERR
43
#define CYGNUM_HAL_INTERRUPT_reserved52
44
#define CYGNUM_HAL_INTERRUPT_AAU_ERR
45
#define CYGNUM_HAL_INTERRUPT_BIU_ERR
46
// *** ATU FIQ sources ***
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