Comtrol eCos - Manual (Page 291)

Chapter 9. HAL Interfaces
Register address
HAL_IO_REGISTER
This type is used to store the address of an I/O register. It will normally be a memory address, an integer port
address or an offset into an I/O space. More complex architectures may need to code an address space plus offset
pair into a single word, or may represent it as a structure.
Values of variables and constants of this type will usually be supplied by configuration mechanisms or in target
specific headers.
Register read
HAL_READ_XXX( register, value )
HAL_READ_XXX_VECTOR( register, buffer, count, stride )
These macros support the reading of I/O registers in various sizes. The XXX component of the name may be UINT8 ,
UINT16 , UINT32 .
HAL_READ_XXX() reads the appropriately sized value from the register and stores it in the variable passed as the
second argument.
HAL_READ_XXX_VECTOR() reads count values of the appropriate size into buffer . The stride controls how
the pointer advances through the register space. A stride of zero will read the same register repeatedly, and a stride
of one will read adjacent registers of the given size. Greater strides will step by larger amounts, to allow for sparsely
mapped registers for example.
Register write
HAL_WRITE_XXX( register, value )
HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )
These macros support the writing of I/O registers in various sizes. The XXX component of the name may be UINT8 ,
UINT16 , UINT32 .
HAL_WRITE_XXX() writes the appropriately sized value from the variable passed as the second argument stored it
in the register.
HAL_WRITE_XXX_VECTOR() writes count values of the appropriate size from buffer . The stride controls
how the pointer advances through the register space. A stride of zero will write the same register repeatedly, and a
stride of one will write adjacent registers of the given size. Greater strides will step by larger amounts, to allow for
sparsely mapped registers for example.
Cache Control
This section contains definitions for supporting control of the caches on the CPU.
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