Document Outline

• MAX 10 FPGA Configuration User Guide
• Contents
• 1. MAX 10 FPGA Configuration Overview
• 2. MAX 10 FPGA Configuration Schemes and Features
  • Configuration Schemes
    • JTAG Configuration
      • JTAG Pins
    • Internal Configuration
      • Internal Configuration Modes
      • Configuration Flash Memory
        • Configuration Flash Memory Sectors
        • Configuration Flash Memory Total Programming Time
      • In-System Programming
        • Real-Time ISP
        • ISP and Real-Time ISP Instructions
      • Initialization Configuration Bits
  • Configuration Features
    • Remote System Upgrade in Dual Compressed Images
      • Remote System Upgrade Flow
      • Remote System Upgrade Circuitry
        • Remote System Upgrade Circuitry Signals
        • Remote System Upgrade Circuitry Input Control
        • Remote System Upgrade Input Register
        • Remote System Upgrade Status Registers
        • Master State Machine
      • User Watchdog Timer
      • Altera Dual Configuration IP Core
    • Configuration Design Security
      • AES Encryption Protection
        • Encryption and Decryption
      • Unique Chip ID
        • Altera Unique Chip ID IP Core
      • JTAG Secure Mode
        • JTAG Secure Mode Instructions
      • Verify Protect
      • JTAG Instruction Availability
      • Configuration Flash Memory Permissions
    • SEU Mitigation and Configuration Error Detection
      • Configuration Error Detection
      • User Mode Error Detection
        • Error Detection Block
        • CHANGE_EDREG JTAG Instruction
      • Error Detection Timing
        • Error Detection Frequency
        • Cyclic Redundancy Check Calculation Timing
      • Recovering from CRC Errors
    • Configuration Data Compression
  • Configuration Details
    • Configuration Sequence
      • Power Up
        • Instant-on
      • Reset
      • Configuration
      • Configuration Error Handling
      • Initialization
      • User Mode
    • MAX 10 Configuration Pins
      • JTAG Pin Sharing Behavior
• 3. MAX 10 FPGA Configuration Design Guidelines
  • Dual-Purpose Configuration Pins
    • Guidelines: Dual-Purpose Configuration Pin
    • Enabling Dual-purpose Pin
  • Configuring MAX 10 Devices using JTAG Configuration
    • JTAG Configuration Setup
    • ICB Settings in JTAG Configuration
  • Configuring MAX 10 Devices using Internal Configuration
    • Selecting Internal Configuration Modes
    • .pof and ICB Settings
      • Auto-Generated .pof
      • .pof Generation through Convert Programming Files
    • Programming .pof into Internal Flash
  • Accessing the Remote System Upgrade Block Through User Interface
  • Error Detection
    • Verifying Error Detection Functionality
    • Enabling Error Detection
    • Accessing Error Detection Block Through User Interface
  • Enabling Data Compression
    • Enabling Compression Before Design Compilation
    • Enabling Compression After Design Compilation
  • AES Encryption
    • Generating .ekp File and Encrypt Configuration File
    • Generating .jam/.jbc/.svf file from .ekp file
    • Programming .ekp File and Encrypted POF File
      • Programming .ekp File and Encrypted .pof Separately
      • Integrate the .ekp into .pof Programming
    • Encryption in Internal Configuration
• 4. MAX 10 FPGA Configuration IP Core Implementation Guides
  • Altera Unique Chip ID IP Core
    • Instantiating the Altera Unique Chip ID IP Core
    • Resetting the Altera Unique Chip ID IP Core
  • Altera Dual Configuration IP Core
    • Instantiating the Altera Dual Configuration IP Core
• 5. Altera Dual Configuration IP Core References
  • Altera Dual Configuration IP Core Avalon-MM Address Map
  • Altera Dual Configuration IP Core Parameters
• 6. Altera Unique Chip ID IP Core References
  • Altera Unique Chip ID IP Core Ports
• A. Additional Information for MAX 10 FPGA Configuration User Guide
  • Document Revision History for MAX 10 FPGA Configuration User Guide