Altera ASI MegaCore Function - Manual (Page 18)

Chapter 4: Functional Description 4–3
Receiver
January 2014 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Deserializer
The serial data stream from the LVDS input buffer is sampled using four different
clocks phase-shifted by 90 from each other. Two out of these four clocks are created
from an on-chip PLL. The two remaining clocks are created by inversion of the PLL
clock outputs and should be 337.5-MHz clocks.
Samples are then all converted to the same clock domain and de-serialized into a
10-bit parallel word. The serial clock that samples the bit stream has to be 5/4 of the
incoming bit (for example, 270-bit rate × 5/4 × 4 sample per clock = 1350 Mbps).
The parallel clock that extracts data from the deserializer is running at 135 MHz.
To achieve timing performance, you must correctly constrain your design, refer to
“Constraints” on page A–1 .
For GX-based devices, you can optionally perform the deserialization in a transceiver.
GX Transceiver
For GX-based devices, in the MegaWizard Plug-In Manager you can select either a
soft-logic transceiver or a GX transceiver. If you are using GX transceivers, they
replace the soft-logic deserializer.
f
For more information on the Stratix IV transceiver, refer to the Stratix IV Device
Handbook .
Oversampling Interface
A 5× over-sampling scheme implements data recovery and bit synchronization,
which corresponds to a sampling rate of 1350 Mbps.
The deserializer provides a fixed frequency sampling of the serial data.
Approximately 5 samples are taken for each bit. These samples are accumulated by
the deserializer and passed to the over-sampling interface in a parallel format. Logic
extracts the data from the sets of samples generated by the deserializer.
Firstly, the transition points within the received word are determined. The ASI
receiver uses these transition points to determine the best sample to extract for each
data bit. The logic continuously realigns to the transition points in the incoming data,
and can adapt to a frequency mismatch between the sampling clock and the incoming
data rate. The extracted samples for each data bit are accumulated into a parallel word
for processing by the rest of the ASI receiver.
Word Aligner
The word aligner is consistently looking for two consecutive comma characters
(K28.5) in the parallel data stream coming out of the over-sampling interface. The
word-aligner computes the matching position and shifts words accordingly.
8B10B Decoder
The 8B10B decoder converts 10-bit wide parallel data from 8B10B codes into 8-bit
wide raw data. The decoder detects special characters, code errors (unused codes),
and disparity errors and signals their presence with various flags.