Development board setup, Setting up the board, Chapter 4. development board setup – Altera Cyclone V GT FPGA User Manual
Page 13: Setting up the board –1
September 2014
Altera Corporation
Cyclone V GT FPGA Development Kit
User Guide
4. Development Board Setup
This chapter explains how to set up the Cyclone V GT FPGA development board and
restore default settings.
Setting Up the Board
To configure and apply power to the board, do the following:
1. The FPGA development board ships with its board switches preconfigured to
support the design examples in the kit. If your board might not be currently
configured with the default settings, follow the instructions in
Switch and Jumper Settings” on page 4–2
before proceeding.
2. The FPGA development board ships with design examples stored in flash
memory. Verify the SW4.3 DIP switch is set to the FACT ON (logic 0) position to
load the design stored in the factory portion of flash memory.
1
The FPGA development board can be powered by the PCIe host adapter or the laptop
power adapter. If you want to power the board by the PCIe host system, plug the
FPGA development card into a standard PCIe connector. Alternatively, to power the
FPGA development board using the laptop power adaptor, do the following two
steps:
3. Connect the +19 V (6.32 A) power supply to the DC Power Jack (J8) on the FPGA
board and plug the cord into a power outlet.
c
Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.
4. Set the POWER switch (SW2) to the ON position. When power is supplied to the
board, blue LED (D21) illuminates indicating that the board has power.
The MAX V device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The SW4.3 DIP switch controls which design to
load. When the switch is in the FACT ON (logic 0) position, the PFL loads the design
from the factory portion of flash memory.
1
The MAX V design resides in the <install
dir>\kits\cycloneVGT_5cgtfd9ef35_fpga\examples\max5 directory.
When configuration is complete, the Config Done LED (D7) illuminates, signaling
that the Cyclone V GT device configured successfully.
f
For more information about the PFL megafunction, refer to the
.