Xcrv, lvds, cmos, Xcrv, lvds, cmos –14 – Altera Cyclone V GT FPGA User Manual

Page 36

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6–14

Chapter 6: Board Test System

Using the Board Test System

Cyclone V GT FPGA Development Kit

September 2014

Altera Corporation

User Guide

XCRV, LVDS, CMOS

The XCRV, LVDS, CMOS groups display the following status information during the
loopback test:

Data rate

—Displays the current data rate in megabytes per second (MBps).

Freq

—Displays the data rate frequency in MHz which is equivalent to MBps.

Bits

—Displays the number of bits transmitted since clicking Start.

Inserted errors

—Displays the number of errors inserted by clicking Insert Error

button.

Detected errors

—Displays the number of bit errors detected by the error checking

circuitry.

BER

—Displays the bit error rate of the interface.

Status

PLL lock

—Displays Yes if the PLL is locked.

Pattern Sync

—Displays Yes if the receiver has detected the input data pattern.

Start—

Starts the PRBS data test and begins to monitor and update screen with live

test results.

Stop

—Stops the PRBS data test.

Insert Error

—Inserts an error into a data stream that is detected by the receiver when

in loopback mode. With the Insert Error, there are differences among the three ports:

XCVR—Inserts 4 errors at 1 click.

LVDS—Inserts 3 errors at 1 click.

CMOS—Inserts 1 error at 1 click.

Clear

—Clears the Detected errors counter.

PMA Setting

—Only available for the XCVR test. This control allows you to make

changes to the PMA parameters that affect the active transceiver interface. The
following settings are available for analysis:

Serial Loopback

—Routes the selected TX output signal back to the RX input

signal on-chip to verify operation without using an external loopback board.

VOD

—Specifies the voltage output differential of the transmitter buffer.

Pre-emphasis tap

Pre

—Not available.

First post

—Specifies the amount of pre-emphasis on the first post tap of the

transmitter buffer.

Second post

—Not available.

Equalizer

—Specifies the setting for the receiver equalizer.

DC gain

—Specifies the DC portion of the receiver equalizer.

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