Altera Nios II Custom - Manual (Page 40)

A–2 Appendix A: Custom Instruction Templates
VHDL Custom Instruction Template
Nios II Custom Instruction User Guide January 2011 Altera Corporation
VHDL Custom Instruction Template
Example A–1 shows a VHDL custom instruction template for an internal register type
custom instruction.
Example A–1. VHDL Custom Instruction Template for Internal Register Logic Type Instruction
-- VHDL Custom Instruction Template File for Internal Register Logic
library ieee;
use ieee.std_logic_1164.all;
entity custominstruction is
port(
signal clk: in std_logic;
-- CPU system clock (required for multicycle or extended multicycle)
signal reset: in std_logic;
-- CPU master asynchronous active high reset
--
(required for multicycle or extended multicycle)
signal clk_en: in std_logic;
-- Clock-qualifier (required for multicycle or extended multicycle)
signal start: in std_logic;
-- Active high signal used to specify that inputs are valid
--
(required for multicycle or extended multicycle)
signal done: out std_logic;
-- Active high signal used to notify the CPU that result is valid
--
(required for variable multicycle or extended variable multicycle)
signal n: in std_logic_vector(7 downto 0);
-- N-field selector (required for extended);
-- Modify width to match the number of unique operations in the instruction
signal dataa: in std_logic_vector(31 downto 0);-- Operand A (always required)
signal datab: in std_logic_vector(31 downto 0);-- Operand B (optional)
signal a: in std_logic_vector(4 downto 0);-- Internal operand A index register
signal b: in std_logic_vector(4 downto 0);-- Internal operand B index register
signal c: in std_logic_vector(4 downto 0);-- Internal result index register
signal readra: in std_logic;
-- Read operand A from CPU (otherwise use internal operand A)
signal readrb: in std_logic;
-- Read operand B from CPU (otherwise use internal operand B)
signal writerc: in std_logic;
-- Write result to CPU (otherwise write to internal result)
signal result: out std_logic_vector(31 downto 0)-- result (always required)
);
end entity custominstruction;
architecture a_custominstruction of custominstruction is
-- local custom instruction signals
begin
-- custom instruction logic (note: external interfaces can be used as well)
-- Use the n[7..0] port as a select signal on a multiplexer
-- to select the value to feed result[31..0]
end architecture a_custominstruction;