Altera Nios II Custom - Manual (Page 41)

Appendix A: Custom Instruction Templates A–3
Verilog HDL Custom Instruction Template Example
January 2011 Altera Corporation Nios II Custom Instruction User Guide
Verilog HDL Custom Instruction Template Example
Example A–2 shows a Verilog HDL custom instruction template for an internal
register type custom instruction.
Example A–2. Verilog HDL Custom Instruction Template for Internal Register Logic Type Instruction
// Verilog Custom Instruction Template File for Internal Register Logic
module custominstruction(
clk, // CPU system clock (required for multicycle or extended multicycle)
reset, // CPU master asynchronous active high reset
// (required for multicycle or extended multicycle)
clk_en,// Clock-qualifier (required for multicycle or extended multicycle)
start, // Active high signal used to specify that inputs are valid
// (required for multicycle or extended multicycle)
done, // Active high signal used to notify the CPU that result is valid
//
(required for variable multicycle or extended variable multicycle)
n, // N-field selector (required for extended)
dataa, // Operand A (always required)
datab, // Operand B (optional)
a,
// Internal operand A index register
b, // Internal operand B index register
c, // Internal result index register
readra,// Read operand A from CPU (otherwise use internal operand A)
readrb, // Read operand B from CPU (otherwise use internal operand B)
writerc,// Write result to CPU (otherwise write to internal result)
result // Result (always required)
);
//INPUTS
inputclk;
inputreset;
inputclk_en;
inputstart;
input[7:0]n;// modify width to match the number of unique operations in the instruction
input[4:0]a;
input[4:0]b;
input[4:0]c;
inputreadra;
inputreadrb;
inputwriterc;
input[31:0]dataa;
input[31:0]datab;
//OUTPUTS
outputdone;
output[31:0]result;
// custom instruction logic (note: external interfaces can be used as well)
// Use the n[7..0] port as a select signal on a multiplexer
//
to select the value to feed result[31..0]
endmodule