Altera Stratix V GX FPGA Development Board - Manual (Page 49)

Chapter 2: Board Components 2–41
Components and Interfaces
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
110 HSMB_A12 2.5-V CMOS D18 Memory address bit
114 HSMB_A13 2.5-V CMOS A19 Memory address bit
116 HSMB_A14 2.5-V CMOS B19 Memory address bit
128 HSMB_A15 2.5-V CMOS C19 Memory address bit
43 HSMB_ADDR_CMD0 2.5-V CMOS M18 Memory address or command
132 HSMB_BA0 2.5-V CMOS E18 Memory bank address bit
134 HSMB_BA1 2.5-V CMOS D19 Memory bank address bit
138 HSMB_BA2 2.5-V CMOS F18 Memory bank address bit
140 HSMB_BA3 2.5-V CMOS E19 Memory bank address bit
151 HSMB_C_N 2.5-V CMOS M15 ODT
149 HSMB_C_P 2.5-V CMOS N15 QVLD
44 HSMB_CASN 2.5-V CMOS R16 Memory address or command
150 HSMB_CKE 2.5-V CMOS G19 Memory address or command
40 HSMB_CLK_IN0 LVDS or 2.5-V AF29 Primary single-ended clock in
98 HSMB_CLK_IN_N1 LVDS or 2.5-V T16 LVDS or CMOS clock in 1
152 HSMB_CSN 2.5-V CMOS H19 Memory address or command
48 HSMB_DM0 2.5-V CMOS U11 Data mask
72 HSMB_DM1 2.5-V CMOS J13 Data mask
102 HSMB_DM2 2.5-V CMOS U12 Data mask
126 HSMB_DM3 2.5-V CMOS H14 Data mask
47 HSMB_DQ0 2.5-V CMOS T12 Memory data bus
49 HSMB_DQ1 2.5-V CMOS R12 Memory data bus
53 HSMB_DQ2 2.5-V CMOS N12 Memory data bus
55 HSMB_DQ3 2.5-V CMOS N13 Memory data bus
59 HSMB_DQ4 2.5-V CMOS M12 Memory data bus
61 HSMB_DQ5 2.5-V CMOS L12 Memory data bus
65 HSMB_DQ6 2.5-V CMOS K12 Memory data bus
67 HSMB_DQ7 2.5-V CMOS J12 Memory data bus
71 HSMB_DQ8 2.5-V CMOS G12 Memory data bus
73 HSMB_DQ9 2.5-V CMOS G13 Memory data bus
77 HSMB_DQ10 2.5-V CMOS F12 Memory data bus
79 HSMB_DQ11 2.5-V CMOS E12 Memory data bus
83 HSMB_DQ12 2.5-V CMOS D12 Memory data bus
85 HSMB_DQ13 2.5-V CMOS C12 Memory data bus
89 HSMB_DQ14 2.5-V CMOS B13 Memory data bus
91 HSMB_DQ15 2.5-V CMOS A13 Memory data bus
101 HSMB_DQ16 2.5-V CMOS U13 Memory data bus
103 HSMB_DQ17 2.5-V CMOS T13 Memory data bus
Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference
(J2)
Schematic Signal Name I/O Standard
Stratix V GX FPGA
Device Pin Number
Description