Altera Stratix V GX FPGA Development Board User Manual

Page 60

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2–52

Chapter 2: Board Components

Memory

Stratix V GX FPGA Development Board

October 2014

Altera Corporation

Reference Manual

Table 2–53

lists the QDRII+ component reference and manufacturing information.

N11

QDRII_D1

1.8-V HSTL Class I

AB16

Write data bus

P10

QDRII_D0

1.8-V HSTL Class I

AD15

Write data bus

B6

QDRII_K_P

1.8-V HSTL Class I

AK14

Write clock P

A6

QDRII_K_N

1.8-V HSTL Class I

AL14

Write clock N

A4

QDRII_WPSn

1.8-V HSTL Class I

AK15

Write port select

B7

QDRII_BWSn0

1.8-V HSTL Class I

AH15

Write byte write select 0

A5

QDRII_BWSn1

1.8-V HSTL Class I

AJ15

Write byte write select 1

P3

QDRII_Q17

1.8-V HSTL Class I

AM19

Read data bus

N3

QDRII_Q16

1.8-V HSTL Class I

AN18

Read data bus

L2

QDRII_Q15

1.8-V HSTL Class I

AP19

Read data bus

K3

QDRII_Q14

1.8-V HSTL Class I

AR18

Read data bus

G3

QDRII_Q13

1.8-V HSTL Class I

AP18

Read data bus

F2

QDRII_Q12

1.8-V HSTL Class I

AR19

Read data bus

E3

QDRII_Q11

1.8-V HSTL Class I

AL18

Read data bus

D3

QDRII_Q10

1.8-V HSTL Class I

AK18

Read data bus

B2

QDRII_Q9

1.8-V HSTL Class I

AJ19

Read data bus

B11

QDRII_Q8

1.8-V HSTL Class I

AH19

Read data bus

C10

QDRII_Q7

1.8-V HSTL Class I

AJ18

Read data bus

E11

QDRII_Q6

1.8-V HSTL Class I

AH18

Read data bus

F11

QDRII_Q5

1.8-V HSTL Class I

AG19

Read data bus

J10

QDRII_Q4

1.8-V HSTL Class I

AG18

Read data bus

K11

QDRII_Q3

1.8-V HSTL Class I

AE19

Read data bus

L11

QDRII_Q2

1.8-V HSTL Class I

AD18

Read data bus

M10

QDRII_Q1

1.8-V HSTL Class I

AE18

Read data bus

P11

QDRII_Q0

1.8-V HSTL Class I

AD17

Read data bus

P6

QDRII_C_P

1.8-V HSTL Class I

AT18

Clock P

R6

QDRII_C_N

1.8-V HSTL Class I

AU18

Clock N

A11

QDRII_CQ_P

1.8-V HSTL Class I

AN19

Echo clock P

A1

QDRII_CQ_N

1.8-V HSTL Class I

AF19

Echo clock N

A8

QDRII_RPSn

1.8-V HSTL Class I

AG15

Read port select

H1

QDRII_DOFFn

1.8-V HSTL Class I

AV13

DLL enable

Table 2–52. QDRII+ Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board Reference

(U5)

Schematic

Signal Name

I/O Standard

Stratix V GX FPGA

Device Pin Number

Description

Table 2–53. QDRII+ Component Reference and Manufacturing Information

Board

Reference

Description

Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U5

QDRII+, 2 M × 18, 550 MHZ

Cypress

CY7C2263KV18-550BZXI

www.cypress.com

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