Hardware features, Software features, Block diagram – Altera Cyclone II FPGA Starter Development Board User Manual

Page 10: Block diagram –2

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Reference Manual

Altera Corporation

Cyclone II FPGA Starter Development Board

October 2006

Introduction

Hardware Features

The development board has the following hardware features:

Altera Cyclone

®

II EP2C20 FPGA device

Altera EPCS4 Serial Configuration device

USB-Blaster controller chip set for programming and user API
control, supporting both JTAG and Active Serial (AS) programming
modes

512-KByte SRAM

8-MByte SDRAM

4-MByte Flash memory

SD Flash Card socket

4 Push button switches

10 Toggle switches

10 Red user LEDs

8 Green user LEDs

50 MHz, 27 MHz, and 24 MHz oscillators for clock sources

24-bit CD-quality audio CODEC with line-in, line-out, and
microphone-in jacks

VGA DAC (4-bit resistor network) with VGA-out connector

RS-232 transceiver and 9-pin connector

PS/2 mouse/keyboard connector

Two 40-pin expansion headers with resistor protection

7.5V DC adapter or a USB cable (provided in the kit) for power

Software Features

Flexible control of the development board and Altera hardware and
software tools provide an effective FPGA-based design environment. In
addition to the hardware features, the development board provides
software support for standard I/O interfaces and a control panel facility
for accessing various components. The kit also provides software for a
number of demonstrations that illustrate the advanced capabilities of the
development board.

Use of the development board requires familiarity with the Altera
Quartus II software. Tutorials for the Quartus II software and for the
Cyclone II FPGA Starter Board are available on the Altera web site or on
the included development kit CD-ROM in the Examples directory.

Block Diagram

The block diagram of the development board (

Figure 1–2

) shows that for

maximum user flexibility, all the blocks connect through the Cyclone II
FPGA device. Thus, the user can implement any system design by
configuring the FPGA.

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