Altera Cyclone II FPGA Starter Development Board - Manual (Page 12)

1–4 Reference Manual Altera Corporation
Cyclone II FPGA Starter Development Board October 2006
Introduction
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For detailed information about the USB-Blaster circuitry, refer to the Cyclone II
FPGA Starter Board schematic found in the BoardDesignFiles / Schematic
directory in the kit installation directory.
AS Programming
In the Active Serial programming method, the configuration bit stream
downloads into the Altera EPCS4 serial EEPROM chip. The EEPROM
provides non-volatile storage of the bit stream, retaining the information
even when power to the Cyclone II FPGA Starter board is turned off.
When the board powers up, the configuration data in the EPCS4 device
automatically loads into the Cyclone II FPGA.
Configuration Procedure
For both the JTAG and AS programming methods, the Cyclone II FPGA
Starter board connects to a host computer via a USB cable. Because of this
connection type, the host computer identifies the board as an Altera
USB-Blaster
device. The following sections describe the JTAG and AS
programming steps.
Configuring the FPGA in JTAG Mode
Figure 1–3 illustrates the JTAG configuration setup. To download a
configuration bit stream into the Cyclone II FPGA, perform the following
steps:
1. Ensure that power is applied to the Cyclone II FPGA Starter board.
2. Connect the supplied USB cable to the USB-Blaster port on the
board.
3. Configure the JTAG programming circuit on the board by setting
the RUN/PROG switch (on the left side of the board) to the RUN
position.
4. To program the FPGA, use the Quartus II Programmer module to
select a configuration bit-stream file with the .sof filename extension.