Altera Cyclone II FPGA Starter Development Board - Manual (Page 13)

Altera Corporation Reference Manual 1–5
October 2006 Cyclone II FPGA Starter Development Board
Introduction
Figure 1–3. JTAG Configuration Setup
Configuring the EPCS4 Device in AS Mode
Figure 1–4 illustrates the AS configuration setup. To download a
configuration bit stream into the EPCS4 serial EEPROM device, perform
the following steps:
1. Ensure that power is applied to the Cyclone II FPGA Starter board.
2. Connect the supplied USB cable to the USB-Blaster port on the
board.
3. Configure the JTAG programming circuit by setting the
RUN/PROG
switch (on the left side of the board) to the PROG
position.
4. To program the EPCS4 device, use the Quartus II Programmer
module to select a configuration bit-stream file with the .pof
filename extension.
5. After the programming operation completes, set the RUN/PROG
switch back to the RUN position.
6. Reset the board by turning the power switch off and then on again.
This action causes the new configuration data in the EPCS4 device
to load into the FPGA chip.
f
Refer to the Serial Configuration Devices chapter in the Altera Configuration
Device Handbook for more information about the EPCS4 device.
USB Blaster Circuit
MAX
3128
USB
FPGA
JTAG Config Port
EPCS Serial
Configuration
Device
RUN/PROG
RUN”
Auto Power on Config