Epson S5U1C63000A - Manual (Page 249)

CHAPTER 8: DEBUGGER
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xdp/xdps
(xilinx fpga data dump)
Function
This command displays the content of the FPGA on the standard peripheral circuit board to the
[Command] window in a 16 words/line hexadecimal dump format.
Format
>xdp <address1> [<address2>]
↵
for main FPGA (direct input mode)
>xdps <address1> [<address2>]
↵
for sub FPGA (direct input mode)
<address1>: Start address to display; hexadecimal
<address2>: End address to display; hexadecimal
Condition:
0
≤
address1
≤
address2
≤
FPGA end address
Examples
If only <address1> is defined, the debugger displays data for 256 words from <address1>.
>xdp 0
↵
Addr +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
00000: FF 84 AB EF F9 D8 FF BB FB BB BF FB BF BF FB BF
00010: BB FB BB BF BB BF FB BB BF BF FB BB FF EE FF EE
00020: EF FE D7 FB FE EE EF EF EE EE FE EE FB FE EF EF
: : :
000E0: FF FF FF FF FB FF FF FF BD DF FB FD DF FF FF FF
000F0: FF FF BF FF FF FF FF F9 FF FF FF FF FF FF FF FF
>
If both <address1> and <address2> are defined, the debugger displays data from <address1> to
<address2>.
>xdp 100 100
↵
Addr +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
00100: FF
>
Notes
• An error results if the specified address is not a hexadecimal number.
Error : invalid value
• An error results if the start address is larger than the end address.
Error : end address < start address
GUI utility
None