Epson S5U1C63000A - Manual (Page 75)

CHAPTER 4: ASSEMBLER
S5U1C63000A MANUAL EPSON 61
(S1C63 FAMILY ASSEMBLER PACKAGE)
4.6 Section Management
4.6.1 Definition of Sections
The memory configuration of the S1C63 Family microcomputer is divided into a code ROM that contains
programs written, and data memories such as data RAM and I/O memory. Moreover, some models carry
a data ROM that holds static data written.
A section refers to an area where codes are written (or to be mapped), and there are three types of sec-
tions in correspondence with the memories:
1. CODE section Area located within a code ROM.
2. DATA section Area located within a data ROM.
3. BSS section Denotes a RAM area.
To allow to specify these sections in a source file, the assembler comes provided with pseudo-instruc-
tions.
CODE section
The .code pseudo-instruction defines a CODE section. Statements from this instruction to another
section defining instruction will be regarded as program codes, and will be so processed as to be
mapped in the code ROM. The source file will be regarded as a CODE section by default. Therefore,
the part that goes from top of the file, to another section will be processed as a CODE section. Because
this section is of 13 bits/word, 4-bit data cannot be defined.
DATA section
The .data pseudo-instruction defines a DATA section. Statements from this instruction to another
section defining instruction will be regarded as 4-bit data, and will be so processed as to be mapped in
the data ROM. Therefore, nothing else can be described in this area other than the symbols for
referring to the address of the data ROM, the 4-bit data defining pseudo-instruction (.word), and
comments. This section is applied only to models having a data ROM.
BSS section
The .bss pseudo-instruction defines a BSS section. Statements from this instruction to another section
defining instruction will be regarded as 4-bit data, and will be so processed as to be mapped in the
data memory (RAM). Therefore, nothing else can be described in this area other than the symbols for
referring to the address of the data memory, the area securing pseudo-instructions (.comm and
.lcomm
).
The .comm pseudo-instruction and the .lcomm pseudo-instruction are designed to define the symbol
and size of a data area. Although the BSS section basically consists in a RAM area, it can as well be
used as a data memory area, such as display memory and I/O memory. Since code definition in this
area is meaningless in embedded type microcomputers, such as those of the S1C63 Family, nothing
else can be described other than the two instructions and comments.
4.6.2 Absolute and Relocatable Sections
The assembler is a relocatable assembler that always generates an relocatable object and needs the linker
to make it into an executable absolute object. However, each section in one source can be absolute or
relocatable depending on how they are described. The section whose absolute address is specified with
the .org pseudo-instruction in the source is an absolute section, while the section whose absolute address
is not specified is an relocatable section. Absolute addresses of relocatable sections will be fixed by the
linker. Both types of sections can be included in one source.