Intel 80960HD - Manual (Page 11)

80960HA/HD/HT
Datasheet 11
subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is
decoupled from the core. This lets the processor execute instructions while the bus performs
memory accesses independently.
The Bus Controller’s key features include:
• Demultiplexed, Burst Bus to support most efficient DRAM access modes
• Address Pipelining to reduce memory cost while maintaining performance
• 32-, 16- and 8-bit modes to facilitate I/O interfacing
• Full internal wait state generation to reduce system cost
• Little and Big Endian support
• Unaligned Access support implemented in hardware
• Three-deep request queue to decouple the bus from the core
• Independent physical and logical address space characteristics
2.2.3 On-Chip Caches and Data RAM
As shown in Figure 1 , the 80960Hx provides generous on-chip cache and storage features to
decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction
cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set
associative. Stores that hit the data cache are written through to memory. The data cache performs
write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly
allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access
every clock cycle.
2.2.4 Priority Interrupt Controller
The interrupt unit provides the mechanism for the low latency and high throughput interrupt
service essential for embedded applications. A priority interrupt controller provides full
programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17
core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within
10 core clocks of the request. When the interrupt has a higher priority than the processor priority,
the context switch to the interrupt routine would typically complete in another seven bus clocks.
External agents post interrupts through the 8-bit external interrupt port. The Interrupt unit also
handles the two internal sources from the Timers. Interrupts may be level- or edge-triggered.
2.2.5 Guarded Memory Unit
The Guarded Memory Unit (GMU) provides memory protection without the address translation
found in Memory Management Units. The GMU contains two memory protection schemes: one
prevents illegal memory accesses, the other detects memory access violations. Both signal a fault
to the processor. The programmable protection modes are: user read, write or execute; and
supervisor read, write or execute.