Intel 80960HD - Manual (Page 68)

80960HA/HD/HT
68 Datasheet
Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
WAIT
D31:0,
CLKIN
A D D D A’ D’ D’
Valid Valid
In-
Valid Valid 01 10 11 00
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
Valid
D
In-
Valid
DP3:0
PCHK
1 2
Burst
Bus
Width
Odd Parity
N
XDA
N
WDD
N
WAD
N
RDD
29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0
Enabled
1
ON
1
X
xxxx
32-Bit X
x
Enabled
1
X
xx
X
xxxxx
0
00
X
x
0
00000
Function
Bit
Value
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
10
PMCON
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin